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------------------------------------------------------------------ Call for...

------------------------------------------------------------------ Call for Papers ------------------------------------------------------------------ 2020 IEEE International Conference on Computer Design (ICCD) Oct 18-21, 2020 Hartford, Connecticut USA -----------------------------------------------------------...

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a...

Hello, I'm dealing with some fast state machines and gate-level-timing simulation of some components has been very helpful. Now using a Cyclone V I found that I can't do timing gate-level timing simulation, quartus does not generate the SDF file, the *.sdo file. Altera/Intel says this on the documentation regarding simulation: "Gate-level timing simulation is supported only for the...

2017 Dennis terminated from the Public Library. Failure to perform guard duties. Last week, the week of June 19th, Dennis was summarily...

2017 Dennis terminated from the Public Library. Failure to perform guard duties. Last week, the week of June 19th, Dennis was summarily discharged from his position of library security guard by new interim librarian, apparently a young woman not to be ?truffled? with. The new librarian cited the primary reason for Officer D?s summary dismissal as a ?failure to act in accorda

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I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box...

I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box on the HDMI output and writes a littel String with white letters on top of it. I want to use it in Intel Quartus environment , do some test-outputs on my screen and finally add some more Hardware to the Avalon system. Unfortunately it doe

Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost hardware description...

Hi folks, Here to talk about PipelineC. https://github.com/JulianKemmerer/PipelineC/wiki What is it?: - C-like almost hardware description language - A compiler that produces VHDL for specific devices/operating frequencies I am looking for: - anyone who wants to help me develop (Python, VHDL, C) - suggestions on how to make PipelineC more useful/new features - project ideas (heyo open...

Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to speak to your EDA...

Need to use your company EDA tools from home, here are some tips: 1) First of all, the most important solution is to speak to your EDA vendor= , I am sure all have solutions for you and some even give you a free tempor= ary license (if you are an existing customer). 2) If you have a node locked license, simply take the dongle home. 3) If you have a MAC based license then try to spoof the MA...

Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using an ATMega...

Hi, I'm trying to program a TinyFPGA BX to provide 3 registers to emulate an FDC9266, the bulk will later be done using an ATMega ucontroller. To sort out the A0,nCS,nRD,nWR,nDACK, I have inserted a code block which should generate the following internal signals: SEL: switch a "Mux 2:1" between the outputs of the STATUS and the DATA IN registers OE: enable a TRI-STATE output to the pr...

Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downto 0); end...

Hi, I have a data record designed as follows: type DATA_RECORD_t record I1: unsigned(7 downto 0); I2: unsigned(15 downto 0); end record; I want to get its bit number and don't want to manually calculate the bit number. How can I do it? Thank you. Weng