arnaud douville (@adouville)
OK...The code in your second question seems to be ok.The only question is how your DUT knows a data is writing to it by the test bench as the 's_E' is not an input...
Hello,Do you remove something in the testbench you enclosed? Because the actual code is a bit strange: no entity, no architecture, ...I suggest you to look at a...
Hello,1. If the Lite version is sufficient, why do you want to pay ;-)See https://www.intel.fr/content/www/fr/fr/software/pr... to see which version matches your...
OK. So I don't think this a licensing error...As the Lite edition can program Cyclone V, it should work...Can you check for Quartus revision in the 'About Quartus...
Hello,The type defined into your package (csv_file_read_pk) is csv_file_reader_type (not csv_file_reader)...
I confess that I don't understand everything...Secondly, as Verilog is not my prefer language (I am more a VHDL expert!), maybe the "address=-1" is not correct...
First of all, there is one clock cycle between the 'input' and the 'output' of your process. So at (100; 50), you compute the pixel which will be available at the...
The last column in black is interesting as it seems to be not authorized in your code (not red, not yellow neither blue). Thus it seems that your code is correct......
You don't need to have a two times faster clock. In your case, you would like to generate one pixel at each clock cycle, and so we need to read one value out of...
ROM generation seems to be OK.One way to resolve the problem is to get rid of (temporarily) the ROM and affect constant values to red/green/blue.red <= 255; //instead...
My question was to be sure my understanding... You would like to display on the monitor a 800x600 black and steady image; like this:____________| ...
Are you sure about your video synchros???I mean that H_SCAN counts from 0 to HTOTAL so 'HTOTAL+1' (1041) clock cycles. I suggest that you replace 'if(H_SCAN ==...
Hello,I don't completely understand your plan...If you use a ROM (Read-Only Memory), why do you want to write RGB values into ROM?As stated by Duhast, it seems that...
Hello,Why don't you use the last version proposed by digikey website? v2.2 code is better coded (no gated clock, no both clock edges and Xilinx accepts BUFFER so...
Hello,Your code is a bit tricky...You generate a 'data_clk' signal on a first clocked process and this signal is used as a clock later.Secondly, 'scl_ena' is generated...
Hum...As this is a clocked process, Out_Data will be evaluated at each rising edge of the clock so the 1-2 seconds are really strange.One idea is that you underconstraint...
Something like this... (not tested, nor simulated!)VHDL is powerfull enough and you can add generic parameter to have a reusable component (generic parameter for MC14514...
Use this form to contact adouville
Before you can contact a member of the *Related Sites:
- You must be logged in (register here)
- You must confirm you email address
