HW R&D engineer in the video field FPGA/VHDL/Boards with 15 years of experience

OK...The code in your second question seems to be ok.The only question is how your DUT knows a data is writing to it by the test bench as the 's_E' is not an input...
Hello,Do you remove something in the testbench you enclosed? Because the actual code is a bit strange: no entity, no architecture, ...I suggest you to look at a...

Re: Quartus Prime Licensing

Reply posted 3 weeks ago (09/30/2020)
Hello,1. If the Lite version is sufficient, why do you want to pay ;-)See https://www.intel.fr/content/www/fr/fr/software/pr... to see which version matches your...
OK. So I don't think this a licensing error...As the Lite edition can program Cyclone V, it should work...Can you check for Quartus revision in the 'About Quartus...
Is there a time_limited.sof file in your quartus directory?
Hello,The type defined into your package (csv_file_read_pk) is csv_file_reader_type (not csv_file_reader)...

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 1 year ago (05/02/2019)
You're welcome... If I can help, it is with great pleaure!

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 1 year ago (04/29/2019)
I confess that I don't understand everything...Secondly, as Verilog is not my prefer language (I am more a VHDL expert!), maybe the "address=-1" is not correct...

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 1 year ago (04/26/2019)
First of all, there is one clock cycle between the 'input' and the 'output' of your process. So at (100; 50), you compute the pixel which will be available at the...

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 1 year ago (04/25/2019)
The last column in black is interesting as it seems to be not authorized in your code (not red, not yellow neither blue). Thus it seems that your code is correct......

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 1 year ago (04/24/2019)
You don't need to have a two times faster clock. In your case, you would like to generate one pixel at each clock cycle, and so we need to read one value out of...

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 2 years ago (04/19/2019)
ROM generation seems to be OK.One way to resolve the problem is to get rid of (temporarily) the ROM and affect constant values to red/green/blue.red <= 255; //instead...

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 2 years ago (04/17/2019)
My question was to be sure my understanding... You would like to display on the monitor a 800x600 black and steady image; like this:____________|         ...

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 2 years ago (04/16/2019)
Are you sure about your video synchros???I mean that H_SCAN counts from 0 to HTOTAL so 'HTOTAL+1' (1041) clock cycles. I suggest that you replace 'if(H_SCAN ==...

Re: Altera Cyclone IV - ROM: 1-Port Problem

Reply posted 2 years ago (04/15/2019)
Hello,I don't completely understand your plan...If you use a ROM (Read-Only Memory), why do you want to write RGB values into ROM?As stated by Duhast, it seems that...

Re: remains a black box sine it has not binding entity

Reply posted 2 years ago (08/29/2018)
Hello,Why don't you use the last version proposed by digikey website? v2.2 code is better coded (no gated clock, no both clock edges and Xilinx accepts BUFFER so...

Re: remains a black box sine it has not binding entity

Reply posted 2 years ago (08/28/2018)
Hello,Your code is a bit tricky...You generate a 'data_clk' signal on a first clocked process and this signal is used as a clock later.Secondly, 'scl_ena' is generated...

Re: 1st project having issues with latches?

Reply posted 3 years ago (09/14/2017)
Hum...As this is a clocked process, Out_Data will be evaluated at each rising edge of the clock so the 1-2 seconds are really strange.One idea is that you underconstraint...

Re: 1st project having issues with latches?

Reply posted 3 years ago (09/13/2017)
Something like this... (not tested, nor simulated!)VHDL is powerfull enough and you can add generic parameter to have a reusable component (generic parameter for MC14514...

Re: 1st project having issues with latches?

Reply posted 3 years ago (09/12/2017)
Hello,You use the FPGA as an asynchronous component... Do you look at timing report? According your coding style, several logic stages will be implemented and depending...

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