remains a black box sine it has not binding entity
Started by 8 years ago●7 replies●latest reply 8 years ago●2485 viewsA VHDL developer encountered a 'black box' warning and synthesis failure in Xilinx ISE 14.7 because a subcomponent could not be bound to its entity. The discussion initially focused on RTL coding style issues, such as gated clocks and the use of the 'BUFFER' type, before identifying a configuration error in the IDE.
The issue was ultimately resolved by correcting the project hierarchy and file associations within the Xilinx ISE workspace, as a conflicting test bench file was preventing the tool from correctly locating the source entity.
- The 'black box' warning often indicates that the synthesis tool cannot find the source file or the entity name does not match the component instantiation.
- File management issues in Xilinx ISE, such as duplicate associations in simulation and implementation views, can cause hierarchy resolution failures.
- Using the 'BUFFER' type in VHDL can lead to synthesis issues with certain tools, and using internal signals is generally recommended.
- RTL design best practices suggest avoiding gated clocks and mixed-edge triggering to ensure hardware compatibility.
HI
I'm working on a design where I have implemented an I2C module which I'm trying to use as a component in another piece of VHDL.
The problem I've got is that when I try and synthesize my design, I get the following warning about the I2C component, "<i2c_master_src> remains a black-box since it has no binding entity." This is the prevents me from implementing the design. I have searched for some information on this to find a solution to this issue, but without success. Can someone please explain what is causing this warning, as I have managed to use components in other VHDL designs without this issue.
The code for the I2C master is in I2C_master_src.vhd, and the code which instantiates the I2C component is in I2C_Main.vhd. The code for I2C main is only in early stages, I haven't completed it yet because of my current problem.
Thanks in advance
Andrew
Hello,
Your code is a bit tricky...
You generate a 'data_clk' signal on a first clocked process and this signal is used as a clock later.
Secondly, 'scl_ena' is generated at both rising and falling edges of the clock.
You use a 'BUFFER' type: some synthesizer does not like this (it is preferable using a 'ack_error_int' signal internally and then perform a 'ack_error <= ack_error_int'.
I recommend that we re-read your code and/or code with a hardware spirit in mind. Otherwise, if you are not familiar with RTL, you can search through internet (you can find several I2C modules expecially on opencores.org).
Arnaud.
Hi Arnaud
Thank you for your reply. I'll take a look at my code again, and re consider / rework the use of buffer.
The code I've used was taken from here
Andrew
Hello,
Why don't you use the last version proposed by digikey website? v2.2 code is better coded (no gated clock, no both clock edges and Xilinx accepts BUFFER so it should be OK using ISE)...
I start an implementation using Vivado 2016.2. It is OK with v2.2 while it is KO with your version...
Moreover, reading the error message: are you sure you indicate 'I2C_Master_src.vhd' as an input file into ISE... It is like ISE does not catch the file???
Arnaud.
I assume i2c_master_src is complete.If the whole module is optimised out by the tool there is a chance of missing entity. If possible could you share the messages spit out by the tool ?
Hi Rajkeerthy18
Thanks for your answer. The message I get from my tool is pasted at the bottom of this post.
I should have said that I'm using Xilinx ISE 14.7, and the device is a xc6slx45t-3fgg484 on a SP605 board.
Kind regards
Andrew
ERROR:NgdBuild:604 - logical block 'i2c_port' with type 'I2C_Master_src' could
not be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, case mismatch between the block name and the edif or ngc file name, or
the misspelling of a type name. Symbol 'I2C_Master_src' is not supported in
target 'spartan6'.
This is the message by builder. You may want to look at Synthesis report and look for warnings. Code seems mixed up with state assignments and output assignments, may have to have separate procedural blocks of each logic.
Hello
I think that part of my problem was due to test bench file in the simulation tab also accessing the file I2C_master_src.vhd In the implementation view the hierachy was showing a question mark for the I2C_master_src.vhd file, removing the test bench file in the simulation view has fixed the "black box" problem.
The synthesis is able to find the file, but there are other issues with the code which I need to work through.
Andrew
