PhD in DSP underwater acoustics and optimal control Thales R&D in active/passive sonars SACET Research on Telecom Physical layers XILINX DSP expert covering half of Europe + India + Australia

Re: Bob Jenkins Hash on FPGA

Reply posted 6 months ago (04/10/2020)
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Re: Bob Jenkins Hash on FPGA

Reply posted 6 months ago (04/08/2020)
Mixing is even easier in logic as shifting are just wire redirection.If your target is a Xilinx SoC/MPSoC/Versal ACAP then give a try to Vitis and Vitis HLS. If...

Re: Suggest a FPGA project

Reply posted 2 years ago (01/07/2019)
1 and (4,5) seems incompatible to me. Furthermore Vivado is not compatible with Virtex 2 Pro. With the latest Xilinx Vivado tools you will be able to target 7-series...

Re: BRAM based FIFO

Reply posted 2 years ago (07/06/2018)
Hihave a look to the UG768  "7 series FPGAs Libraries Guide"   p60You'll have the template to instantiate the right FIFO.Olivier

Re: Implementing octave algorithm in FPGA using c++

Reply posted 2 years ago (06/20/2018)
Contact me oliviert@xilinx.com

Re: Implementing octave algorithm in FPGA using c++

Reply posted 2 years ago (06/20/2018)
The same way you can use: C, C++, Python, Compiled Python, Java, ... to program your processor.The same question could be asked!The thing is that each language suits...

Re: Xilinx IPs for DFT, FFT, LTE_FFT

Reply posted 2 years ago (04/25/2018)
As says martinthompson The LTE FFT contains this 1536, which adds a radix-3 stage in the FFT. If you want to be able to change dynamically the FFT size you will...

Re: Which FPGA kit to start with in 2018?

Reply posted 3 years ago (03/25/2018)
On the XILINX side you should restrict yourself to 7-series and beyond to be able to take advantage of the Vivado tool.The first choice is: do you want a pure FPGA,...

Re: DSP Windowing function

Reply posted 3 years ago (08/30/2017)
I couldn't say a better advice!Try Vivado HLS from Xilinx, you'll get what you need in a few minutes.

Re: FPGA - ML & DL

Reply posted 3 years ago (08/16/2017)
adamt99 is right. reVision and RAS support machine learning (inference side) using Caffee network description using int8 and int16.Another area is the reduced precision...

Re: Programmable SoC and SoC FPGA

Reply posted 3 years ago (04/27/2017)
Hi all,I had a look to Internet:https://en.wikipedia.org/wiki/PSoChttp://www.cypress.com/products/32-bit-arm-cortex-...PSoC or Programmable SoC is the term used...

Re: Programmable SoC and SoC FPGA

Reply posted 3 years ago (04/25/2017)
In standard SoC (or programmable SoC) you have fixed IOs, fixed hardware accelerators that you can access from within a processor.Xilinx and Intel PSG (formerly...
@cfelton IPI (Xilinx) is not mandatory to create a design. It is just another way to create a hardware design. It's been designed to integrate high-level blocks...
Hi,I think you should first package your own Verilog IPs into IPXact and then recreate the block design.In order to do so you have the User Guide UG1119 and the...

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