It hashes arbitrary size string and outputs an integer seed. I would like to implement the this Jenkins hash on FPGA. Please help me in following questions
- What should be my fundamental RTL design parameters for this hash to be implemented on FPGA? I mean I am looking for most basic considerations that should be taken into account. Looking for a starting point.
- What could be the challenges (if any)?
I would be really happy to have some helping answers.
The data base terminology in your link directly maps to fpga, the terminology becomes:
keys = inputs to your design
hash function: logic for mapping those inputs to address of memory (index)
hash table : memory (or registers)
In fpgas memory is of limited size, you may also consider registers, are more expensive but allow simulataneous multiple indexing at same time.
So in short you can directly implement what you want on fpga but with limited memory size yet it can be fast and even access all array in one clock period if that is needed.
Ok thanks....And what about the mixing step involved in the code? How can mixing be implemented?
Mixing is even easier in logic as shifting are just wire redirection.
If your target is a Xilinx SoC/MPSoC/Versal ACAP then give a try to Vitis and Vitis HLS. If it is a Xilinx FPGA give a chance to Vivado HLS (pretty soon replaced by Vitis HLS).
You can start by just giving the C-code to the tool, and then can think about optimization.
Thanks a lot ! Do Vivado HLS has some examples on Jenkins Hash?