Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per...

Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per clock and a performance metric incorporating all three. I don't recall the author's name, but it was amazingly complete. Anyone remember that? Still got the link? -- Rick C. - Get 1,000 miles of free Supercharging - T

I tireid using ust a pin pair and inverting function. But with LVCMOS333 on Breakout Board ( 3,3V for I/O), MachXO implements hysteresis on...

I tireid using ust a pin pair and inverting function. But with LVCMOS333 on Breakout Board ( 3,3V for I/O), MachXO implements hysteresis on input and this seems to hamper the oscillations. I can't start the crystal reliably. If oscillation starts, it runs fine. I used siimple 24MHz quartz with 1M across and 22pF toward GND on each side. Can't find anythong on the matter on Lattice... ...

Just a few days ago, they presented Certus-NX series that is based on their new Nexus platform. Has anyone here been testing these and what...

Just a few days ago, they presented Certus-NX series that is based on their new Nexus platform. Has anyone here been testing these and what else can we expect on 28nm ? Will there be ECP3 and XO3 successor with Nexus ? I've contacted Lattice, but so far received no formal response.

I've always found it awkward that when I create a project the various tempo= rary files the tool creates are at the top of the project tree and...

I've always found it awkward that when I create a project the various tempo= rary files the tool creates are at the top of the project tree and my files= are down at the end of a branch of the subdirectory tree. This sees so up= side down to me. I should be able to put all my source files in a simple d= irectory in the main project folder with all the tool specific files in a s= eparate di...

I can't do it. Every time I try, LSE reports "combinatorial loop" and optimizes whole thing away. I tried using attributes syn_preserve,...

I can't do it. Every time I try, LSE reports "combinatorial loop" and optimizes whole thing away. I tried using attributes syn_preserve, syn_keep and syn_noprune, but the result is the same. LSE Manual doesn't seem to list any more tricks that I could use or so it seems. IS there any specific trick for this ? I want to implement it to get a feeling about performance of some internal...

Seen over on Hacker News: https://tomverbeure.github.io/2020/06/14/AHA363-Reverse-Engineering.html I bought one, just for the fact that it...

Seen over on Hacker News: https://tomverbeure.github.io/2020/06/14/AHA363-Reverse-Engineering.html I bought one, just for the fact that it provides a convenient PCIe board to experiment with. Even if I have to hot-air the custom ICs off the board, it is still a useful experimentation platform. --- Zach

I'm clearly failing to understand how enums are supposed to work in SystemVerilog. I've created a header file with the enum definition. I...

I'm clearly failing to understand how enums are supposed to work in SystemVerilog. I've created a header file with the enum definition. I `include that header file in two files that want to use the common definition. Vivado complains that the values are multiply defined. If I remove the `include from one of the files, then the enum values aren't defined in that file and Vivado complains...

Hello, I'm a collector and tinkerer of old, archaic devices, and I recently came across a MMI M2018-20CP (date code 81xx) in a PGA...

Hello, I'm a collector and tinkerer of old, archaic devices, and I recently came across a MMI M2018-20CP (date code 81xx) in a PGA package. I've found the M2064 data sheet, but I can't seem to track down the M2018 data sheet from MMI/AMD. I'm also looking for the MMI XACT tools of the same era that would support generating the data pattern (what we might call a configuration bitstr...

Hello,=20 For those of you who do DSP modeling in Python, I've recently released a pa= ckage that supports fixed point arithmetic. The...

Hello,=20 For those of you who do DSP modeling in Python, I've recently released a pa= ckage that supports fixed point arithmetic. The existing open source tools = are lackluster and MATLAB doesn't nicely fit into our simulation/testing wo= rkflow. Just trying to get the word out for a higher adoption rate! Documentation is here: https://fixedpoint.readthedocs.io Gihub repo is here: ...

Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification?...

Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification? I'm getting into FPGA development and have created a simple filter. I wanted to test it out on audio data that I can generate and see that the filter actually works, but I haven't found a way to actually "pass" data to a design. Thanks Moh