MyHDL synthesis: from browser to FPGA in five seconds
Martin Strubel walks through how modern open-source tooling slashes the pain of converting super-HDLs into FPGA-ready firmware. Instead of long translation chains from MyHDL or nMigen into Verilog or VHDL, yosys and its Python API let you build synthesizeable primitives on the fly, inspect schematics, and emit synthesized Verilog or firmware quickly. The post explains the shift from toolchain friction to fast browser-to-FPGA workflows.
Using GHDL for interactive simulation under Linux
Martin walks through using the free GHDL VHDL simulator on Linux to go beyond static testbenches and run interactive simulations. You will see how GHDL and gtkwave give a fast, low-cost waveform workflow, how to call C code from VHDL via the VHPI interface, and how simple pipes let real software talk to your simulated FPGA for deeper system-level debugging.
Using GHDL for interactive simulation under Linux
Martin walks through using the free GHDL VHDL simulator on Linux to go beyond static testbenches and run interactive simulations. You will see how GHDL and gtkwave give a fast, low-cost waveform workflow, how to call C code from VHDL via the VHPI interface, and how simple pipes let real software talk to your simulated FPGA for deeper system-level debugging.
MyHDL synthesis: from browser to FPGA in five seconds
Martin Strubel walks through how modern open-source tooling slashes the pain of converting super-HDLs into FPGA-ready firmware. Instead of long translation chains from MyHDL or nMigen into Verilog or VHDL, yosys and its Python API let you build synthesizeable primitives on the fly, inspect schematics, and emit synthesized Verilog or firmware quickly. The post explains the shift from toolchain friction to fast browser-to-FPGA workflows.
Using GHDL for interactive simulation under Linux
Martin walks through using the free GHDL VHDL simulator on Linux to go beyond static testbenches and run interactive simulations. You will see how GHDL and gtkwave give a fast, low-cost waveform workflow, how to call C code from VHDL via the VHPI interface, and how simple pipes let real software talk to your simulated FPGA for deeper system-level debugging.
MyHDL synthesis: from browser to FPGA in five seconds
Martin Strubel walks through how modern open-source tooling slashes the pain of converting super-HDLs into FPGA-ready firmware. Instead of long translation chains from MyHDL or nMigen into Verilog or VHDL, yosys and its Python API let you build synthesizeable primitives on the fly, inspect schematics, and emit synthesized Verilog or firmware quickly. The post explains the shift from toolchain friction to fast browser-to-FPGA workflows.
