I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
MyHDL Presentation Examples
Christopher Felton collected slide-ready MyHDL demos he used at EELive and PyOhio, making it easy to see practical HDL examples in action. The post explains the tradeoffs behind single-slide examples, links to 2013 and 2014 demos from simple FPGA hello-worlds to filters and a VGA system, and points readers to the repository where full and larger examples live for reuse.
[Comments] C HLS Benefits
Christopher Felton argues C-to-gate HLS showed little advantage in his median calculation comparison with MyHDL. He explains the test mixes language paradigm and abstraction: Vivado C HLS is an imperative, step-by-step style while MyHDL offers a concurrent, HDL-level description with Python's readability and elaboration features. He notes C-HLS can help if you only know C, but for massively parallel FPGA work non-C tools may be preferable.
MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
Introducing the VPCIe framework
Simulating an embedded CPU and FPGA together is painful when PCI Express is in the middle, so Fabien Le Mentec built VPCIe to virtualize that link. VPCIe traps PCIe accesses from a QEMU-hosted CPU and forwards them to a GHDL-driven VHDL simulation using TCP, letting you run unmodified Linux and drivers against your hardware model. The project is open source on GitHub and supports remote or concurrent device simulations.
Tool install for examples
The post explains the toolchain and installs needed to compile the FPGARelated MyHDL examples. It notes that examples use MyHDL for hardware description and the myhdl_tools/rhea.build Python packages to drive the FPGA vendor tools, so the full flow runs from a Python environment. The author lists required installs: MyHDL (pip or GitHub), myhdl_tools (Bitbucket), the rhea.build automation package, and the FPGA vendor toolchains (Xilinx ISE WebPACK, Altera Quartus, Lattice Diamond). Board-specific programming utilities such as fpgalink and xstools are also required for various development boards. Most examples live in a Bitbucket repository or gist and include a test_and_build_.py script that automates convert, synthesize, map, place-and-route, and bitfile generation. A 2015 changelog notes some tools were deprecated and repository locations were updated.
How to start in FPGA development? - Simulation software tools
Nuria Orduna lays out a pragmatic approach to FPGA simulation, comparing Xilinx ISE with integrated ModelSim against a three-tool flow with ModelSim and Precision. She explains why independent ModelSim runs and using notepad++ for VHDL can speed debugging, and why Precision and CoreGen conversions can be painful. Read for a compact, practiced workflow to simplify simulation, synthesis, and project organization.
FPGA Assemblers and Time Machines
Modern FPGA toolchains have turned tinkering into a slog, Victor Yurkovsky recalls the old joy of manual hardware hacking and wants it back. He proposes an assembler-style approach, exemplified by the proposed 'fpgasm', that preserves placement and routing, programs bitstreams in seconds, and makes live probing and rapid iteration practical again. Read this to see why low-level control could revive hands-on FPGA learning.
Are you kidding me?
Christopher Felton pushes back on the idea that C/C++/SystemC are the natural path to higher-abstraction FPGA design. He argues hardware designers often do not use C-family languages for modeling and simulation, so choosing C as the HLS lingua franca may be more about tool momentum than suitability. The post urges reconsidering languages with higher abstraction and lower cost of entry for system modeling and HLS.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
Using GHDL for interactive simulation under Linux
Martin walks through using the free GHDL VHDL simulator on Linux to go beyond static testbenches and run interactive simulations. You will see how GHDL and gtkwave give a fast, low-cost waveform workflow, how to call C code from VHDL via the VHPI interface, and how simple pipes let real software talk to your simulated FPGA for deeper system-level debugging.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Introducing the VPCIe framework
Simulating an embedded CPU and FPGA together is painful when PCI Express is in the middle, so Fabien Le Mentec built VPCIe to virtualize that link. VPCIe traps PCIe accesses from a QEMU-hosted CPU and forwards them to a GHDL-driven VHDL simulation using TCP, letting you run unmodified Linux and drivers against your hardware model. The project is open source on GitHub and supports remote or concurrent device simulations.
How to start in FPGA development? - Simulation software tools
Nuria Orduna lays out a pragmatic approach to FPGA simulation, comparing Xilinx ISE with integrated ModelSim against a three-tool flow with ModelSim and Precision. She explains why independent ModelSim runs and using notepad++ for VHDL can speed debugging, and why Precision and CoreGen conversions can be painful. Read for a compact, practiced workflow to simplify simulation, synthesis, and project organization.
FPGA Assemblers and Time Machines
Modern FPGA toolchains have turned tinkering into a slog, Victor Yurkovsky recalls the old joy of manual hardware hacking and wants it back. He proposes an assembler-style approach, exemplified by the proposed 'fpgasm', that preserves placement and routing, programs bitstreams in seconds, and makes live probing and rapid iteration practical again. Read this to see why low-level control could revive hands-on FPGA learning.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
Tool install for examples
The post explains the toolchain and installs needed to compile the FPGARelated MyHDL examples. It notes that examples use MyHDL for hardware description and the myhdl_tools/rhea.build Python packages to drive the FPGA vendor tools, so the full flow runs from a Python environment. The author lists required installs: MyHDL (pip or GitHub), myhdl_tools (Bitbucket), the rhea.build automation package, and the FPGA vendor toolchains (Xilinx ISE WebPACK, Altera Quartus, Lattice Diamond). Board-specific programming utilities such as fpgalink and xstools are also required for various development boards. Most examples live in a Bitbucket repository or gist and include a test_and_build_.py script that automates convert, synthesize, map, place-and-route, and bitfile generation. A 2015 changelog notes some tools were deprecated and repository locations were updated.
Are you kidding me?
Christopher Felton pushes back on the idea that C/C++/SystemC are the natural path to higher-abstraction FPGA design. He argues hardware designers often do not use C-family languages for modeling and simulation, so choosing C as the HLS lingua franca may be more about tool momentum than suitability. The post urges reconsidering languages with higher abstraction and lower cost of entry for system modeling and HLS.
[Comments] C HLS Benefits
Christopher Felton argues C-to-gate HLS showed little advantage in his median calculation comparison with MyHDL. He explains the test mixes language paradigm and abstraction: Vivado C HLS is an imperative, step-by-step style while MyHDL offers a concurrent, HDL-level description with Python's readability and elaboration features. He notes C-HLS can help if you only know C, but for massively parallel FPGA work non-C tools may be preferable.
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
Using GHDL for interactive simulation under Linux
Martin walks through using the free GHDL VHDL simulator on Linux to go beyond static testbenches and run interactive simulations. You will see how GHDL and gtkwave give a fast, low-cost waveform workflow, how to call C code from VHDL via the VHPI interface, and how simple pipes let real software talk to your simulated FPGA for deeper system-level debugging.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
How to start in FPGA development? - Simulation software tools
Nuria Orduna lays out a pragmatic approach to FPGA simulation, comparing Xilinx ISE with integrated ModelSim against a three-tool flow with ModelSim and Precision. She explains why independent ModelSim runs and using notepad++ for VHDL can speed debugging, and why Precision and CoreGen conversions can be painful. Read for a compact, practiced workflow to simplify simulation, synthesis, and project organization.
FPGA Assemblers and Time Machines
Modern FPGA toolchains have turned tinkering into a slog, Victor Yurkovsky recalls the old joy of manual hardware hacking and wants it back. He proposes an assembler-style approach, exemplified by the proposed 'fpgasm', that preserves placement and routing, programs bitstreams in seconds, and makes live probing and rapid iteration practical again. Read this to see why low-level control could revive hands-on FPGA learning.
Introducing the VPCIe framework
Simulating an embedded CPU and FPGA together is painful when PCI Express is in the middle, so Fabien Le Mentec built VPCIe to virtualize that link. VPCIe traps PCIe accesses from a QEMU-hosted CPU and forwards them to a GHDL-driven VHDL simulation using TCP, letting you run unmodified Linux and drivers against your hardware model. The project is open source on GitHub and supports remote or concurrent device simulations.
Tool install for examples
The post explains the toolchain and installs needed to compile the FPGARelated MyHDL examples. It notes that examples use MyHDL for hardware description and the myhdl_tools/rhea.build Python packages to drive the FPGA vendor tools, so the full flow runs from a Python environment. The author lists required installs: MyHDL (pip or GitHub), myhdl_tools (Bitbucket), the rhea.build automation package, and the FPGA vendor toolchains (Xilinx ISE WebPACK, Altera Quartus, Lattice Diamond). Board-specific programming utilities such as fpgalink and xstools are also required for various development boards. Most examples live in a Bitbucket repository or gist and include a test_and_build_.py script that automates convert, synthesize, map, place-and-route, and bitfile generation. A 2015 changelog notes some tools were deprecated and repository locations were updated.
Are you kidding me?
Christopher Felton pushes back on the idea that C/C++/SystemC are the natural path to higher-abstraction FPGA design. He argues hardware designers often do not use C-family languages for modeling and simulation, so choosing C as the HLS lingua franca may be more about tool momentum than suitability. The post urges reconsidering languages with higher abstraction and lower cost of entry for system modeling and HLS.
[Comments] C HLS Benefits
Christopher Felton argues C-to-gate HLS showed little advantage in his median calculation comparison with MyHDL. He explains the test mixes language paradigm and abstraction: Vivado C HLS is an imperative, step-by-step style while MyHDL offers a concurrent, HDL-level description with Python's readability and elaboration features. He notes C-HLS can help if you only know C, but for massively parallel FPGA work non-C tools may be preferable.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
