MyHDL synthesis: from browser to FPGA in five seconds
When it comes to feeding (mostly proprietary) synthesis tools, the most widely supported HDL (hardware design language) is probably plain Verilog, then comes VHDL. The reasons for that are simply based on popularity or the fact that VHDL is a little more complex to parse.
So, all super-HDLs (like Chisel, SpinalHDL, etc.) transfer to one of these V* HDLs in one way or another, then synthesis/mapping/place'n'route turns it into a wiring map for the silicon. Same went for MyHDL or its also...
Summer of gateware is coming (again)
How time flies! I swear my last post was a summary of the 2015 summer of gateware. This year (2016) MyHDL is participating in the Google summer of code again, for the second year, continuing as a sub-org of the Python Software Foundation organization.
This year, so far, has been amazing and inspiring. We have had many talented students inquire about the project and contribute to myhdl and
Summer of Gateware
This (last) summer the MyHDL project participated in the Google Summer of Code (GSoC) as a sub-organization under the Python Software Foundation (PSF). This was our first year participating - there was a lot for us to learn. Overall it was a worthwhile and beneficial activity.
Being a first time sub-org we were limited to a maximum of two students. We had nine students apply and twelve mentors volunteer. Only being able to select two students...
I don’t often convert VHDL to Verilog but when I do ...
VHDL to VerilogI don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement). For the most part I am HDL agnostic. Well that is not true, I have a strong preference for MyHDL, and an insubstantial preference for VHDL over Verilog. The choice of HDL for a project is often complicated, irrational, sometimes rational, but most often random. It is often not a choice of the developer - for...
Point of View
I was caught of guard when someone commented:
"when a FIR filter is full of multiple loops and complex code, something is wrong"The comment was made during an informal discussion on alternative hardware description languages (HDL) and was targeted to the straightforward FIR filter implemented in MyHDL:
(different FIR description simulation results)
Personally, (and...
MyHDL Presentation Examples
The last two years I presented at EELive. The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper]. The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL. I also presented at a regional Python conferene: pyohio. At the Python conference I presented...
[Comments] C HLS Benefits
Earlier this week I posted a small write-up comparing a hardware median calculation implemented in a C-to gates "HLS" (Vivado C HLS) and a version in MyHDL. For a long time I have had the belief that C-to-gate technologies are of little to no benefit - based on the simple premise that "C" is not that high-level of a language (I actually consider it lower than Verilog and VHDL ... but that is a conversation for another time).
Language comparisons...
MyHDL Interface Example
MyHDL Interfaces ExampleWith the next release of MyHDL, version 0.9, conversion of interfaces will be supported. In this context an interface is any object with a Signal attribute. This can be used to simplify connection between modules and port definitions. For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:
class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...MyHDL @EDAPlayground
Trying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.
The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.
There are a couple examples...
binary hello world
Python + Ohio + MyHDL + FPGARecently I had the opportunity to coordinate a hands-on programmable hardware (FPGA) workshop (open-space) at a regional Python conference - @pyohio. The workshop was for those that had little to no exposure to programmable hardware. For this situation I used two basic examples: two versions of a binary hello world.
The binary hello world -- blinking an LED -- is a good starting point to introduce programmable hardware, hardware descriptions languages,...
I don’t often convert VHDL to Verilog but when I do ...
VHDL to VerilogI don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement). For the most part I am HDL agnostic. Well that is not true, I have a strong preference for MyHDL, and an insubstantial preference for VHDL over Verilog. The choice of HDL for a project is often complicated, irrational, sometimes rational, but most often random. It is often not a choice of the developer - for...
MyHDL Resources and Projects
Last updated 07-Nov-2017
MyHDL ResourcesIf you want to dive into MyHDL (digital hardware description in Python) there are many resources available. Below is a list of MyHDL resources, including some of the past blogs here on fpgarelated.
The MyHDL manual is a great (probably the best) place to get started.
The manual is an in-depth introduction to MyHDL. The concepts are well explained and there are examples to test while working through the...
MyHDL @EDAPlayground
Trying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.
The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.
There are a couple examples...
binary hello world
Python + Ohio + MyHDL + FPGARecently I had the opportunity to coordinate a hands-on programmable hardware (FPGA) workshop (open-space) at a regional Python conference - @pyohio. The workshop was for those that had little to no exposure to programmable hardware. For this situation I used two basic examples: two versions of a binary hello world.
The binary hello world -- blinking an LED -- is a good starting point to introduce programmable hardware, hardware descriptions languages,...
Point of View
I was caught of guard when someone commented:
"when a FIR filter is full of multiple loops and complex code, something is wrong"The comment was made during an informal discussion on alternative hardware description languages (HDL) and was targeted to the straightforward FIR filter implemented in MyHDL:
(different FIR description simulation results)
Personally, (and...
MyHDL synthesis: from browser to FPGA in five seconds
When it comes to feeding (mostly proprietary) synthesis tools, the most widely supported HDL (hardware design language) is probably plain Verilog, then comes VHDL. The reasons for that are simply based on popularity or the fact that VHDL is a little more complex to parse.
So, all super-HDLs (like Chisel, SpinalHDL, etc.) transfer to one of these V* HDLs in one way or another, then synthesis/mapping/place'n'route turns it into a wiring map for the silicon. Same went for MyHDL or its also...
MyHDL Interface Example
MyHDL Interfaces ExampleWith the next release of MyHDL, version 0.9, conversion of interfaces will be supported. In this context an interface is any object with a Signal attribute. This can be used to simplify connection between modules and port definitions. For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:
class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...[Comments] C HLS Benefits
Earlier this week I posted a small write-up comparing a hardware median calculation implemented in a C-to gates "HLS" (Vivado C HLS) and a version in MyHDL. For a long time I have had the belief that C-to-gate technologies are of little to no benefit - based on the simple premise that "C" is not that high-level of a language (I actually consider it lower than Verilog and VHDL ... but that is a conversation for another time).
Language comparisons...
Summer of Gateware
This (last) summer the MyHDL project participated in the Google Summer of Code (GSoC) as a sub-organization under the Python Software Foundation (PSF). This was our first year participating - there was a lot for us to learn. Overall it was a worthwhile and beneficial activity.
Being a first time sub-org we were limited to a maximum of two students. We had nine students apply and twelve mentors volunteer. Only being able to select two students...
Summer of gateware is coming (again)
How time flies! I swear my last post was a summary of the 2015 summer of gateware. This year (2016) MyHDL is participating in the Google summer of code again, for the second year, continuing as a sub-org of the Python Software Foundation organization.
This year, so far, has been amazing and inspiring. We have had many talented students inquire about the project and contribute to myhdl and
I don’t often convert VHDL to Verilog but when I do ...
VHDL to VerilogI don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement). For the most part I am HDL agnostic. Well that is not true, I have a strong preference for MyHDL, and an insubstantial preference for VHDL over Verilog. The choice of HDL for a project is often complicated, irrational, sometimes rational, but most often random. It is often not a choice of the developer - for...
MyHDL Resources and Projects
Last updated 07-Nov-2017
MyHDL ResourcesIf you want to dive into MyHDL (digital hardware description in Python) there are many resources available. Below is a list of MyHDL resources, including some of the past blogs here on fpgarelated.
The MyHDL manual is a great (probably the best) place to get started.
The manual is an in-depth introduction to MyHDL. The concepts are well explained and there are examples to test while working through the...
binary hello world
Python + Ohio + MyHDL + FPGARecently I had the opportunity to coordinate a hands-on programmable hardware (FPGA) workshop (open-space) at a regional Python conference - @pyohio. The workshop was for those that had little to no exposure to programmable hardware. For this situation I used two basic examples: two versions of a binary hello world.
The binary hello world -- blinking an LED -- is a good starting point to introduce programmable hardware, hardware descriptions languages,...
MyHDL synthesis: from browser to FPGA in five seconds
When it comes to feeding (mostly proprietary) synthesis tools, the most widely supported HDL (hardware design language) is probably plain Verilog, then comes VHDL. The reasons for that are simply based on popularity or the fact that VHDL is a little more complex to parse.
So, all super-HDLs (like Chisel, SpinalHDL, etc.) transfer to one of these V* HDLs in one way or another, then synthesis/mapping/place'n'route turns it into a wiring map for the silicon. Same went for MyHDL or its also...
MyHDL Interface Example
MyHDL Interfaces ExampleWith the next release of MyHDL, version 0.9, conversion of interfaces will be supported. In this context an interface is any object with a Signal attribute. This can be used to simplify connection between modules and port definitions. For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:
class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...MyHDL ... MyPWM
The PWM topic appears to be popular lately on the fpgarelated site. This is coincidence, but I typically find the topic of modulating and demodulating signals interesting. For digital systems it is always entertaining to play with PWMs. The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin. The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).
As...
Tool install for examples
Most of my examples on fpgarelated use MyHDL for the hardware description and another Python package myhdl_tools rhea.build to control the FPGA vendor's software. This means everything is controlled and run from the Python environment.
Install the following to compile the posted examples:
MyHDL package : pip myhdl or myhdl github myhdl_tools : myhdl_tools bitbucket rhea...Summer of gateware is coming (again)
How time flies! I swear my last post was a summary of the 2015 summer of gateware. This year (2016) MyHDL is participating in the Google summer of code again, for the second year, continuing as a sub-org of the Python Software Foundation organization.
This year, so far, has been amazing and inspiring. We have had many talented students inquire about the project and contribute to myhdl and
Point of View
I was caught of guard when someone commented:
"when a FIR filter is full of multiple loops and complex code, something is wrong"The comment was made during an informal discussion on alternative hardware description languages (HDL) and was targeted to the straightforward FIR filter implemented in MyHDL:
(different FIR description simulation results)
Personally, (and...
[Comments] C HLS Benefits
Earlier this week I posted a small write-up comparing a hardware median calculation implemented in a C-to gates "HLS" (Vivado C HLS) and a version in MyHDL. For a long time I have had the belief that C-to-gate technologies are of little to no benefit - based on the simple premise that "C" is not that high-level of a language (I actually consider it lower than Verilog and VHDL ... but that is a conversation for another time).
Language comparisons...
