Use DPLL to Lock Digital Oscillator to 1PPS Signal
●3 commentsIntroduction There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency...
Summer of gateware is coming (again)
How time flies! I swear my last post was a summary of the 2015 summer of gateware. This year (2016) MyHDL is participating in the Google summer of code again, for the second year, continuing as a sub-org of the Python...
Makefiles for Xilinx Tools
Building a bitstream from an HDL is a complicated process that requires the cooperation of a lot of tools. You can hide behind an IDE or grow a pair and use command line tools and a makefile to tie your build process together. I am...
I don’t often convert VHDL to Verilog but when I do ...
VHDL to Verilog I don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement). For the most part I am HDL agnostic. Well that is not true, I have a strong...
MyHDL @EDAPlayground
●1 commentTrying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL. The...
BGA and QFP at Home 1 - A Practical Guide.
It is almost universally accepted by the hobbyists that you can't work with high-density packages at home. That is entirely incorrect. I've been assembling and reflowing BGA circuit boards at home for a few years now. BGAs and...
How FPGAs work, and why you'll buy one
●2 commentsToday, pretty much everyone has a CPU, a DSP and a GPU, buried somewhere in their PC, phone, car, etc. Most don't know or care that they bought any of these, but they did. Will everyone, at some future point, also buy an FPGA? The market size...
StrangeCPU #4. Microcode
Summary: Sliding windows containing runs of microcode. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2: Sliding-Window Token Machines, an...
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Summary: Decoding instructions with a Sliding Window system. 0-Bit Sliding Register Windows. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2:...
StrangeCPU #2. Sliding Window Token Machines
Summary: An in-depth exploration of Sliding Window Token Machines; ARM notes. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2: Sliding-Window Token...
I don’t often convert VHDL to Verilog but when I do ...
VHDL to Verilog I don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement). For the most part I am HDL agnostic. Well that is not true, I have a strong...
Makefiles for Xilinx Tools
Building a bitstream from an HDL is a complicated process that requires the cooperation of a lot of tools. You can hide behind an IDE or grow a pair and use command line tools and a makefile to tie your build process together. I am...
StrangeCPU #4. Microcode
Summary: Sliding windows containing runs of microcode. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2: Sliding-Window Token Machines, an...
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Summary: Decoding instructions with a Sliding Window system. 0-Bit Sliding Register Windows. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2:...
StrangeCPU #1. A new CPU
Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even...
StrangeCPU #2. Sliding Window Token Machines
Summary: An in-depth exploration of Sliding Window Token Machines; ARM notes. Table of Contents: Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes. Part 2: Sliding-Window Token...
New Design - Finally!
For those of you who are familiar with my work, you already know that FPGARelated.com is not the only engineering web site that I publish. I also publish DSPRelated.com and EmbeddedRelated.com. Those two web sites have been on a new design for...
MyHDL @EDAPlayground
●1 commentTrying out MyHDL became a little easier recently. MyHDL is now avaialbe @EDAPlayground. One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL. The...
Use DPLL to Lock Digital Oscillator to 1PPS Signal
●3 commentsIntroduction There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency...
Summer of gateware is coming (again)
How time flies! I swear my last post was a summary of the 2015 summer of gateware. This year (2016) MyHDL is participating in the Google summer of code again, for the second year, continuing as a sub-org of the Python...
