How to do Math's in FPGA - Using VHDL 2008

Adam Taylor

Following the introduction of VHDL 93, which introduced the numeric_std package and the signed and unsigned types, implementing fixed point maths has been fairly straight forward. Using this package, we can implement mathematics using a fixed point representation. However, to implement a fixed point algorithm we need to understand the simple rules regarding fixed point operations.

Agile Testing on an Embedded Field Programmable Gate Array Platform

Todor Vlaev

Agile software methodologies are the state of art methodologies used on current software projects. Testing is one of the main pillars of agile development and many of the practices are common among various flavours of the methodologies. Despite their wide-spread adoption in different domains, agile testing practices still seem to be a novel concept on embedded programming projects. This is specifically true when it comes to hardware design modeling. Thus, the goal of this project was to introduce the main concepts of agile testing and demonstrate their application on an Field Programmable Gate Array (FPGA) platform. The project was conceptually divided into two parts. The first one was the design and implementation of an FPGA development board. The second part focused on developing hardware design modules with a suitable hardware description language and ultimately building a contained testing system to demonstrate the most important agile testing practices. The result of the first phase was a working FPGA development board and an Ethernet extension board. During the second phase example hardware models were designed with MyHDL. Unit tests were implemented before the actual modules, thus adopting a testdriven development (TDD) approach. The tests were automated with the help of a continuous integration server. A viable process for a functional testing routine was also outlined. Based on the outcomes, it can be concluded that agile testing practices can be successfully utilized even in the specific domain of digital design. The natural continuation of this project would be the implementation of the suggested functional testing routine.

Implementing the Nintendo Entertainment System on a FPGA

Jonathan Sieber

In this work I try to implement the Nintendo Entertainment System (NES) on a FPGA platform. The NES is one of the most famous video game consoles of the 8-bit era. Using custom designed hardware that was primarily optimized for low cost, and was not very powerful at that time, it still was the basis for a big library of high quality games, that are still fun to play today. Besides being a practical exercise in hardware design, this project aims to be a continuation of the efforts of the emulator scene, to conserve video game history by bringing it to new hardware platforms.

Introducing the Spartan 3E FPGA and VHDL

Mike Field

I want to help hackers take the plunge into the world of FPGAs-- Starting at purchasing an FPGA development board, and all the way through the process of getting their first project up and running. In this eBook, we will discuss the low level details of working with FPGAs, rather than diving straight into the System on a Chip (SOAC) level.

FPGAs for Dummies - Altera Special Edition

Andrew Moore

Field programmable gate arrays (FPGAs) are integrated circuits that enable designers to program customized digital logic in the field. FPGAs have been around since the 1980s and were originally conceived to give all design teams the ability to create custom logic. In the early days, using an FPGA in your design meant you had to do a lot of programming just to get your FPGA to perform simple functions, so most designers avoided them. If you haven’t looked into FPGAs since your university studies way back when, you’ll want to take another look at them. The FPGA has evolved from a useful but humble interface device into a system-level integrated circuit (IC) with its own microprocessors, memory blocks, and interfaces. It’s the next big thing. Now would be a great time to get an inexpensive development kit, download free tools, and begin to explore this world for yourself. And this book will help you understand the practical uses of FPGAs.

VHDL Tutorial

Peter J. Ashenden
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The purpose of this tutorial is to describe the modeling language VHDL. VHDL includes facilities for describing logical structure and function of digital systems at a number of levels of abstraction, from system level down to the gate level. It is intended, among other things, as a modeling language for specification and simulation. We can also use it for hardware synthesis if we restrict ourselves to a subset that can be automatically translated into hardware.

Introduction to Verilog

Peter M. Nyasulu

Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. The other one is VHDL. HDL’s allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology-independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits.

FPGA Implementation of Digital Filters

Chi-Jui Chou

Digital Filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application-specific integrated circuits (ASICs) for higher rates. This paper describes an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs). The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate approaches. Since many current FPGA architectures are in-system programmable, the configuration of the device may be changed to implement different functionality if required. Our examples illustrate that the FPGA approach is both flexible and provides performance comparable or superior to traditional approaches.

Architecture of FPGAs and CPLDs: A Tutorial

Stephen Brown
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This paper provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs). We first define the relevant terminology in the field and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips, and give examples of applications of each type of device.

Implementing video compression algorithms on reconfigurable devices

Stewart, Graeme

The increasing density offered by Field Programmable Gate Arrays(FPGA), coupled with their short design cycle, has made them a popular choice for implementing a wide range of algorithms and complete systems. In this thesis the implementation of video compression algorithms on FPGAs is studied. Two areas are specifically focused on; the integration of a video encoder into a complete system and the power consumption of FPGA based video encoders. Two FPGA based video compression systems are described, one which targets surveillance applications and one which targets video conferencing applications. The FPGA video surveillance system makes use of a novel memory format to improve the efficiency with which input video sequences can be loaded over the system bus. The power consumption of a FPGA video encoder is analyzed. The results indicating that the motion estimation encoder stage requires the most power consumption. An algorithm, which reuses the intra prediction results generated during the encoding process, is then proposed to reduce the power consumed on an FPGA video encoder’s external memory bus. Finally, the power reduction algorithm is implemented within an FPGA video encoder. Results are given showing that, in addition to reducing power on the external memory bus, the algorithm also reduces power in the motion estimation stage of a FPGA based video encoder.