High-level synthesis

Started by Benjamin Couillard in comp.arch.fpga3 months ago 28 replies

It's been about 3 years since I've done any *serious* FPGA work. I used mostly VHDL or sometimes my own Matlab scripts to create automated VHDL...

It's been about 3 years since I've done any *serious* FPGA work. I used mostly VHDL or sometimes my own Matlab scripts to create automated VHDL files. I would like to know if anyone has used High-level synthesis recetnly for *real* work and if so, would they recommend that people learn it?


TCS34725 Basys3 VHDL

Started by Anonymous in comp.arch.fpga3 months ago 1 reply

Hi I am trying to use TCS34725 to identify Green and Red Colors, it has I2C interface and i could not find any I2C interface about this and i am...

Hi I am trying to use TCS34725 to identify Green and Red Colors, it has I2C interface and i could not find any I2C interface about this and i am not capable to write a protocol code what should I do I am stucked. I just need when it sees green it turns one led and when it sees red it turns another led.


Hello

Started by Anonymous in comp.arch.fpga3 months ago 3 replies

Hi all, New to this list. I'm Gerard, Ham Radio operator F6EEQ. I have a Papilio Pro(Xilinx Spartan 6 LX)development platform since 5 or 6...

Hi all, New to this list. I'm Gerard, Ham Radio operator F6EEQ. I have a Papilio Pro(Xilinx Spartan 6 LX)development platform since 5 or 6 years. But did not di much with it. Read an article in G-QRP club magazine "SPRAT" about DDS with FPGA and this renewed my interest. Hope to find much help and info here. See you soon. Gerard


Tiny CPUs for Slow Logic

Started by Anonymous in comp.arch.fpga3 months ago 62 replies

Most of us have implemented small processors for logic operations that don't need to happen at high speed. Simple CPUs can be built into an FPGA...

Most of us have implemented small processors for logic operations that don't need to happen at high speed. Simple CPUs can be built into an FPGA using a very small footprint much like the ALU blocks. There are stack based processors that are very small, smaller than even a few kB of memory. If they were easily programmable in something other than C would anyone be interested?


Xilinx M1 Pad file

Started by A.P.Richelieu in comp.arch.fpga3 months ago

Is there anyone that has a description of the Xilinx M1 Pad file syntax? An example file would do as well. Best Regards AP

Is there anyone that has a description of the Xilinx M1 Pad file syntax? An example file would do as well. Best Regards AP


Color sensor with BASYS3 VHDL

Started by Anonymous in comp.arch.fpga3 months ago 1 reply

Hi, I need to make a circuit which does the following thing: When it sees a red object it will send output 0 until it sees a green objec= t...

Hi, I need to make a circuit which does the following thing: When it sees a red object it will send output 0 until it sees a green objec= t (like a well colored cubic toy), after it sees green it will send output = 1 until it sees red again. ( If it is hard to implement I'm ok with just ou= tput 0 when it sees red and outputs 1 when it sees green, I mean it is ok i= f the outputs not contin...


Anyone have files from the old Xilinx FTP?

Started by Tim Regeant in comp.arch.fpga3 months ago 5 replies

Hi all, Looking for someone who has FTP files from 1997 for the XACT Foundation v6.0.2 update. Web Archive has the files listed here:...

Hi all, Looking for someone who has FTP files from 1997 for the XACT Foundation v6.0.2 update. Web Archive has the files listed here: https://web.archive.org/web/19970616112705/http://www.xilinx.com/support/techsup/ftp/htm_index/s w_foundation.htm Anyone capture these files? Thanks.


Implementation of Modbus Slave using only FPGA, without any softcore

Started by Swapnil Patil in comp.arch.fpga3 months ago 9 replies

Hello Folks, I wanted to Implement Modbus Slave protocol with the use of only FPGA, without use of any external or internal softcore,Hardcore....

Hello Folks, I wanted to Implement Modbus Slave protocol with the use of only FPGA, without use of any external or internal softcore,Hardcore. Currently i have successfully Implemented Modbus Master protcol, Now I am Looking forward to bulit Modbus Slave as well. For Implementation Of Modbus Slave I am currently using Spartan6 FPGA and ISE 14.7 for For coding In VHDl. I want some hel...


Green/Red detector and button controlled car (BASYS3/VHDL)

Started by Anonymous in comp.arch.fpga3 months ago

Hi, I am a 2nd-year ee student, and I need to make a term Project. With BASYS3 by using VHDL. My purpose is constructing a car which can be...

Hi, I am a 2nd-year ee student, and I need to make a term Project. With BASYS3 by using VHDL. My purpose is constructing a car which can be controlled with the buttons on BASYS3 ( I think I need Bluetooth module for it to RC a car). In addition to that my car should stop when it sees red ( i think I should use a color sensor for it) and should not work until it sees a green. These


Cyclone V decimation

Started by Piotr Wyderski in comp.arch.fpga4 months ago 14 replies

Hi, the input signal is 14 bits signed@750ksps. I would like to decimate it by a modest factor of ~3000. What would be the best way of doing...

Hi, the input signal is 14 bits signed@750ksps. I would like to decimate it by a modest factor of ~3000. What would be the best way of doing it on a Cyclone V, resource-wise? My usual approach would be a cascade of CIC decimators followed by a FIR corrector, but since there are the DSP blocks, I don't feel it to be the "right" (albeit correct) approach. I'm new to the V family and lack...


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