CAN Sniffer on Altera DE2-115 Board

Started by Ryo Kato in comp.arch.fpga2 months ago

Hi there, I am trying to implement a CAN sniffer on an Altera DE2-115 evaluation board with the Terrasic AD/DA data conversion card (High Speed...

Hi there, I am trying to implement a CAN sniffer on an Altera DE2-115 evaluation board with the Terrasic AD/DA data conversion card (High Speed Mezzanine Card (HSMC) via SMA. I am using two A/D channels for CAN_H and CAN_L bus signals. Before testing it with real CAN signals I want to make sure that the connection is right in terms of voltage swing, differential termination and peak


verilog reg usage

Started by promach in comp.arch.fpga2 months ago 1 reply

Does

Does


Sharing VHDL Verification IP

Started by Espen Tallaksen in comp.arch.fpga2 months ago

Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community has previously been difficult because there was no standardised way of...

Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community has previously been difficult because there was no standardised way of interfacing to and controlling these VVCs. A solution on this challenge could easily reduce the project verification time by 20 to 80%, and at the same time improve the FPGA quality. The open source UVVM has over the last two years standard


engineered data path versus inferred data path

Started by Anonymous in comp.arch.fpga3 months ago 5 replies

Seem to get better results when using inferred data paths? E.g. letting the synthesis tools insert the multiplexers where they see fit gives...

Seem to get better results when using inferred data paths? E.g. letting the synthesis tools insert the multiplexers where they see fit gives better Fmax than laying out the datapath in complete detail. Also don't need to remember and code all the control signals for the muxes. Still code intermediate adders and such to keep the number of inferred carry chains down. Comments? Jim Brakefi...


Xilinx Custom IP accessing 16-bit bram

Started by Norman Lo in comp.arch.fpga3 months ago

Hello, I have used Xilinx core generator to synthesize a bram with width of 16 bit and depth of 80k, resulting a 17-bit address. Let's call...

Hello, I have used Xilinx core generator to synthesize a bram with width of 16 bit and depth of 80k, resulting a 17-bit address. Let's call them bram_data, and bram_addr. I am connecting the bram to PLB bus which has 32-bit address (Bus2IP_Addr) and 32-bit data (Bus2IP_Data). I am not sure how to connect those two together since I don't understand that if the address is not at the...


the FPGA one-shot

Started by John Larkin in comp.arch.fpga3 months ago 13 replies

I finally got a test case for my FPGA async one-shot idea, hacked into a build for something else. I got 17 different one-shots, with various...

I finally got a test case for my FPGA async one-shot idea, hacked into a build for something else. I got 17 different one-shots, with various pin locations and speed/drive strength settings. https://www.dropbox.com/s/4hxena27mpbpg54/FPGA_OS_1.JPG?raw=1 Most of the outputs look like this, with remarkably consistent timing, edges within a few hundred ps. This is typical: https://ww...


Altera Cyclone V SoC availability...

Started by Brane2 in comp.arch.fpga4 months ago 1 reply

I can't find it anywhere. No one carries Cyclone V SX/T, only plain E or Gx...

I can't find it anywhere. No one carries Cyclone V SX/T, only plain E or Gx...


Microsemi now Microchip

Started by HT-Lab in comp.arch.fpga4 months ago 5 replies

In case anybody missed it: https://www10.edacafe.com/nbc/articles/1/1569384/Microchip-Technology-Acquire-Microsemi Hans www.ht-lab.com

In case anybody missed it: https://www10.edacafe.com/nbc/articles/1/1569384/Microchip-Technology-Acquire-Microsemi Hans www.ht-lab.com


How to handle a data packet while calculating CRC.

Started by yogesh tripathi in comp.arch.fpga4 months ago 21 replies

Hi, I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a

Hi, I'm trying to process a Ethernet type package. Suppose if i have detected SFD and now have a


HDL simple survey - what do you actually use

Started by john in comp.arch.fpga4 months ago 33 replies

I'm trying to decide on which to use for a project as the main default that may include a number of freelance people. can you say which of...

I'm trying to decide on which to use for a project as the main default that may include a number of freelance people. can you say which of these you actually use (the most) and have the best skills in Verilog systemVerilog SystemC VHDL Other And if possible what type of work you use it for in general I dont need to know why you use a particular one - and to avoid flame wars ...


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