Is it illegal to use an (enum) as a Verilog function input?

Started by Kevin Simonson in comp.arch.fpga6 months ago 1 reply

I'm still very much interested in finding out whether or not it's possible for a Verilog function to have a boolean value as input, but while I...

I'm still very much interested in finding out whether or not it's possible for a Verilog function to have a boolean value as input, but while I was waiting for input on that I decided to rewrite a version of my Verilog code to use an (enum) instead of a (boolean). Much to my amazement, it appears that I can't use an (enum) as an input to a function either! I wrote the following code


Can anyone explain "cannot currently create a parameter of type" compilation error message?

Started by Kevin Simonson in comp.arch.fpga6 months ago 5 replies

I've written a piece of code with inputs (left) and (right) and output (result), each of which operand is a single bit, which returns a logical...

I've written a piece of code with inputs (left) and (right) and output (result), each of which operand is a single bit, which returns a logical one in (result) if (left) has the same value as (right), and returns a logical zero otherwise. My code is: [code] module ModGc ( result, left, right); output result; input left, right; typedef enum { L_NOT, L_NAND, L_NOR } GateType; typedef stru...


Non-binary NCO Modulus

Started by Rick C in comp.arch.fpga6 months ago 8 replies

I recall digging deeply into NCO design some years ago. I am trying to remember the dirty details of what I had learned. In particular I have a...

I recall digging deeply into NCO design some years ago. I am trying to remember the dirty details of what I had learned. In particular I have a non-binary modulus. I'd like to find the simplest way to implement this. This is the best I can think of now, but I want to say someone had come up with a really nice way to code this that was optimally simple and produced optimally simp


Can a Verilog function take a boolean argument?

Started by Kevin Simonson in comp.arch.fpga6 months ago 1 reply

I've got a Verilog function that I'd like to behave slightly differently depending on the value of a boolean argument, an argument whose value can...

I've got a Verilog function that I'd like to behave slightly differently depending on the value of a boolean argument, an argument whose value can be either (true) or (false). I tried: [code] module sid (); function integer execOp; input integer left; input integer right; input boolean add; begin execOp = add ? left + right : left * right; end endfunction endmodu...


DE10 Standard Audio Demos not working

Started by Nandan Dayal in comp.arch.fpga6 months ago 5 replies

Hello, I bought the DE10 Standard and am having issues trying to run the demos related to audio. I am trying to run the two demos,...

Hello, I bought the DE10 Standard and am having issues trying to run the demos related to audio. I am trying to run the two demos, DE10_Standard_Audio, and DE10_Standard_i2sound, while connecting apple headphones to line out, and 3.5 lavalier microphone to mic in, but I am not able to record anything and play it back for the 1st demo, and I don't hear anything when I speak into t


Trenz FPGA Module

Started by Rick C in comp.arch.fpga6 months ago 5 replies

I'm interested in the Trenz FPGA Module with the Gowin GW1NR-LV9QN88 on board. The price is a bit high... well, I guess not for FPGA products,...

I'm interested in the Trenz FPGA Module with the Gowin GW1NR-LV9QN88 on board. The price is a bit high... well, I guess not for FPGA products, but certainly for the size and costs in making the board. It consists of the FPGA, two power regulators, an FT2232 JTAG/serial port chip, a 4 Kbit EEPROM chip for the FT2232 and a 64M-bit flash chip for the FPGA, two oscillators and powe


Active HDL and the Case of the Haunted Cursor

Started by Rick C in comp.arch.fpga6 months ago 1 reply

Active HDL is really starting to piss me off. I can't understand some of t= he things it does. Now the cursor won't stay where I put it. It...

Active HDL is really starting to piss me off. I can't understand some of t= he things it does. Now the cursor won't stay where I put it. It keeps mov= ing to the end of the simulation a few seconds after I let go of it, or EVE= N IF I'M STILL HOLDING ONTO IT!!! I can drag it around as much as I like. It will snap to changes in a signa= l, but at some point it will snap back to the end o...


Go To VHDL Resource

Started by Rick C in comp.arch.fpga6 months ago 2 replies

I started a new design the other day and realized I had forgotten which web sites were good VHDL resources. There are resources for the language,...

I started a new design the other day and realized I had forgotten which web sites were good VHDL resources. There are resources for the language, there are good resources for the many libraries and there are good resources for style and techniques. What is your favorite? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209 ...


Are Gowin Serious Contenders?

Started by Rick C in comp.arch.fpga6 months ago 7 replies

I'm looking at using Gowin in a design and I not sure about them. They are being sold at Mouser, but the prices are not so great. Their cheapest...

I'm looking at using Gowin in a design and I not sure about them. They are being sold at Mouser, but the prices are not so great. Their cheapest 1 kLUT chips are not too bad at $3@1k, but from there the prices run up quickly, $8@1k for the 4 kLUT device. I thought they had a 2 kLUT device but not at Mouser. Edge Electronics lists the 4 kLUT device for $3.50 qty 1. I've writt


What is a Processor and Software in Context of Reliability Analysis?

Started by Rick C in comp.arch.fpga6 months ago 2 replies

How is a "processor" defined when considering requirements on developing a = design? A project I am on is shoving software into HDL to design an...

How is a "processor" defined when considering requirements on developing a = design? A project I am on is shoving software into HDL to design an FPGA w= hich is being considered "hardware". I'm not fighting it because FPGAs are= what I do. Board level design is a necessary evil to support the FPGA. If= not for the desire to make approval easier the FPGA would not be on the bo= ard.=20 ...


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