MyHDL Presentation Examples
The last two years I presented at EELive. The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper]. The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL. I also presented at a regional Python conferene: pyohio. At the Python conference I presented a brief introduciton to FPGAs and MyHDL.
Generating examples for presentations can be challenging. The examples need to be digestable but interesting. Ideally they fit on a single slide and are readable. The examples attempt to find a balance between brevity and complexity. Because these examples are embedded in the presentation they can be lost over time and the presentations typically only include a snapshot of the example. The following are the links to the examples, some of the examples are versions of earlier fpgarelated posts.
- Strober [eelive ex.]
- IIR Filter [eelive ex.] [fpgareleated]
- FPGA Hello World [pyohio ex.][fpgareleated]
- Add and Scale [eelive ex.]
- Greatest Common Denomimator [eelive ex.]
- Sum of Products [eelive ex.]
- Median [eelive ex.] [fpgarelated]
- VGA System [eelive ex.]
Note, the last two were not actually presented but were included in the repo as larger examples (i.e. not digestable in a single slide).
To post reply to a comment, click on the 'reply' button attached to each comment. To post a new comment (not a reply to a comment) check out the 'Write a Comment' tab at the top of the comments.
Registering will allow you to participate to the forums on ALL the related sites and give you access to all pdf downloads.