Summer of gateware is coming (again)
Wondering what gateware will come out of this summer? Christopher Felton announces MyHDL is back in Google Summer of Code and has been awarded six student slots. Projects span GEMAC, a Leros tiny processor, JPEG encoder front/backends, RISC-V tooling and HDMI+RISC-V work. Follow along for short project updates and a final summer summary.
Summer of Gateware
Christopher Felton walks through MyHDL's first year as a Google Summer of Code sub organization, from selecting two students to shipping SDRAM and conversion work. He highlights the practical bumps, including proposal expectations, the value of early patches, and the need for frequent mentoring and flexible milestones. The post shares concrete lessons for mentors, students, and projects planning to participate in GSoC.
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
Point of View
Christopher defends a straightforward MyHDL RTL description of a FIR filter, arguing it is explicit, readable, and concise. He compares that style to a functional hardware description built with Python primitives and list comprehensions, and finds both convert to identical synthesis resources for this example. The post highlights readability tradeoffs and suggests choice often comes down to background and preference.
MyHDL Presentation Examples
Christopher Felton collected slide-ready MyHDL demos he used at EELive and PyOhio, making it easy to see practical HDL examples in action. The post explains the tradeoffs behind single-slide examples, links to 2013 and 2014 demos from simple FPGA hello-worlds to filters and a VGA system, and points readers to the repository where full and larger examples live for reuse.
[Comments] C HLS Benefits
Christopher Felton argues C-to-gate HLS showed little advantage in his median calculation comparison with MyHDL. He explains the test mixes language paradigm and abstraction: Vivado C HLS is an imperative, step-by-step style while MyHDL offers a concurrent, HDL-level description with Python's readability and elaboration features. He notes C-HLS can help if you only know C, but for massively parallel FPGA work non-C tools may be preferable.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
binary hello world
Christopher Felton walks through two minimalist "binary hello world" examples that make FPGA basics approachable using Python and MyHDL. Attendees wire a button to an LED, add a flip-flop to introduce registers, then implement debouncing and blink-rate control, all compiled with simple Python scripts that drive the FPGA tool flow. Complete source is available on Bitbucket for hands-on experimentation.
MyHDL FPGA Tutorial I (LED Strobe)
Skip Verilog and try MyHDL, a Python-based HDL, to build and simulate an FPGA LED strobe in this hands-on tutorial. Christopher Felton walks through a parameterized LED shifter, py.test driven verification, and automated conversion to Verilog and bitstreams for several development boards. The post includes scripts to generate pin constraints and run vendor tools so you can build and program boards from one language.
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
The Spartans
Christopher Felton walks through the Spartan6 FPGA basics, explaining CLBs, slices, and the new 6-input LUTs while comparing them to Spartan3. He ran timing-driven mappings of real gateware to show practical LUT utilization differences. The post gives a pragmatic estimate of expected LUT savings and points out where mapping results can vary depending on the design.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
binary hello world
Christopher Felton walks through two minimalist "binary hello world" examples that make FPGA basics approachable using Python and MyHDL. Attendees wire a button to an LED, add a flip-flop to introduce registers, then implement debouncing and blink-rate control, all compiled with simple Python scripts that drive the FPGA tool flow. Complete source is available on Bitbucket for hands-on experimentation.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
MyHDL Resources and Projects
Christopher Felton has pulled together a compact, practical guide to learning and using MyHDL, with the essential manual, Jan Decaluwe's deep dives, presentations, example projects, and active Git/Bitbucket repos. Whether you want a tutorial path, reference reads, or hands-on FPGA projects from simple LEDs to SDR and DSP cores, this curated list points you to vetted resources and real designs to study and reuse.
MyHDL FPGA Tutorial I (LED Strobe)
Skip Verilog and try MyHDL, a Python-based HDL, to build and simulate an FPGA LED strobe in this hands-on tutorial. Christopher Felton walks through a parameterized LED shifter, py.test driven verification, and automated conversion to Verilog and bitstreams for several development boards. The post includes scripts to generate pin constraints and run vendor tools so you can build and program boards from one language.
I don’t often convert VHDL to Verilog but when I do ...
Converting VHDL to Verilog is tedious, and Christopher Felton lays out a pragmatic, repeatable workflow using vhd2vl to do most of the heavy lifting. He walks through the iterate-run-comment-fix cycle, highlights frequent failure points like arrays, records and packages, and explains why many open-source projects favor Verilog for better FOSS simulator support.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
Little to no benefit from C based HLS
Christopher shows why C-based HLS delivers little practical benefit compared with a MyHDL RTL approach, using a Vivado HLS median-filter example. He walks through the sort-network median, compares C and MyHDL implementations, and argues MyHDL is as concise while providing clearer microarchitecture control. The post emphasizes that choosing the right algorithm is the hard part, and HLS won’t replace hardware understanding.
MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)
Christopher Felton walks through connecting an FPGA to a TI AIC23 audio codec using MyHDL, covering SPI register programming and I2S streaming. The post explains how the AIC23 module decodes I2S into parallel samples with a Ts sample-valid strobe and how startup SPI writes configure sample width and rate. You get a simple loopback/echo testbench and practical notes on 16/24/32-bit sample handling.
The Spartans
Christopher Felton walks through the Spartan6 FPGA basics, explaining CLBs, slices, and the new 6-input LUTs while comparing them to Spartan3. He ran timing-driven mappings of real gateware to show practical LUT utilization differences. The post gives a pragmatic estimate of expected LUT savings and points out where mapping results can vary depending on the design.
MyHDL Resources and Projects
Christopher Felton has pulled together a compact, practical guide to learning and using MyHDL, with the essential manual, Jan Decaluwe's deep dives, presentations, example projects, and active Git/Bitbucket repos. Whether you want a tutorial path, reference reads, or hands-on FPGA projects from simple LEDs to SDR and DSP cores, this curated list points you to vetted resources and real designs to study and reuse.
binary hello world
Christopher Felton walks through two minimalist "binary hello world" examples that make FPGA basics approachable using Python and MyHDL. Attendees wire a button to an LED, add a flip-flop to introduce registers, then implement debouncing and blink-rate control, all compiled with simple Python scripts that drive the FPGA tool flow. Complete source is available on Bitbucket for hands-on experimentation.
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
