I have only one clock in my design and the number of clock load in my clock report(.par) does not correspond to the number of the registers in the map report(.mrp), does anyone knows the reason?
Clock load is a physical quantity, and is different from the number of registers but depends on the path. There could be fewer sequential elements but depending on layout/location hence path, the loading could be a higer number and vice versa.
Thanks for your response, but i'm still a bit confused. I thought the clock load was the number of registers that used the clock, so I couldn't figure it out how it could be higher than the number of registers.
Is my definition of clock load wrong?
I've got an answer from Lattice, here it is:
"In general, each slice contenting 2 registers and 1 loading clock. So in a perfect condition, 1 clock will load 2 register. However, due to the routing, design implementation, synthesis algorithm and any other design constraints, some slices might use one register only and that’s why these two numbers are mot matching or exactly double."