FPGA Design Engineer

Re: Timing paths from wires to registers

Reply posted 1 month ago (11/09/2019)
I have already indicated those timing paths. What I am questioning is the behavior of the tool itself. Vivado timing does not report warning of unconstrained paths...

Timing paths from wires to registers

New thread started 1 month ago
Hi All,I 've come across this case (please see figure below) .I have a synchronous system but four constants (A,B,C,D) are implemented on wires and any one of them...

Re: Lattice MachXO2 Timing errors.

Reply posted 3 months ago (08/30/2019)
what you described using counters is clock division and is common practice.Your counter may be too wide (23 bits I guess) and thus fails timing on 133MHz clock....

Re: Lattice MachXO2 Timing errors.

Reply posted 3 months ago (08/29/2019)
you got setup timing violations (not exactly clock spec issue). I also notice you have gated the clock down to very low speed. My feeling is that your design is...

Re: Reusing registers in VHDL FSM code

Reply posted 5 months ago (07/03/2019)
I suggest you use one clocked process for FSM or you might as well just use a counter instead of explicit state machine. include all assignment in the clocked process...

Re: Reusing registers in VHDL FSM code

Reply posted 5 months ago (07/03/2019)
Now I see your flag signal is not in clocked process so my first post needs correction but I see you have combinatorial feedback on R1

Re: recovery/removal violations, does it always matter?

Reply posted 6 months ago (06/20/2019)
Yes nothing happens until some input arrives to kick start states or counters...etc. You don't have to release activity immediately just because reset is released....

Re: recovery/removal violations, does it always matter?

Reply posted 6 months ago (06/19/2019)
When state changes immediately on reset release then we are doing work. What I mean by "not doing anything at start" is that literally we don't... such that the...

Re: FPGA output pulsating in real time

Reply posted 6 months ago (06/15/2019)
You will need full debugging on all inputs/outputs from ADC to mixer to filter to observation tool. Otherwise it is all guess work. Pulsating waveform could be generated...

Re: recovery/removal violations, does it always matter?

Reply posted 6 months ago (06/09/2019)
Thanks but again I am not asking about basic textbook definitions and micro details.I am simply asking this "Does it matter if a design is not doing anything at...

Re: recovery/removal violations, does it always matter?

Reply posted 6 months ago (06/08/2019)
Hi Adamt99,Thanks for the reply but if the design does not do anything at start so how metastability could occur if no signal is transitioning. Then if it does occur...
Hi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...

Re: metastabilty with multicycle

Reply posted 7 months ago (05/18/2019)
I see your point valid. I don't have the answer. One might say the latch edge is either enabled or not but this doesn't explain it since enable is not mandatory...

Re: A Law compression for FPGA

Reply posted 1 year ago (08/23/2018)
I follow the LTE standards for radio to ethernet packets. I Don't have choices here.Anyway It turned out that documented table is ok for positive range. For negative...

Re: A Law compression for FPGA

Reply posted 1 year ago (08/23/2018)
I did first convert negative values to unsigned(though that is not stated in the doc) then all negative values were opposite in trend. So I removed the conversion...

Re: A Law compression for FPGA

Reply posted 1 year ago (08/23/2018)
Hi Josy,Thanks for the reply. I haven't access to code right now but I shifted the 13 bits table towards MSB then kept the same pattern. for example the lowest table...

A Law compression for FPGA

New thread started 1 year ago
Hi all,Referring to this doc on A law compression (table 1):http://www.young-engineering.com/docs/YoungEnginee...The table is meant for 13 bits signed to 8 bits...

Re: Xilinx IPs for DFT, FFT, LTE_FFT

Reply posted 2 years ago (04/24/2018)
Thanks for that Martin but I noticed the same option for 1536 is available with fft ip setup.Moreover I assume they could have done one ip for DFT and fft and lte...

Xilinx IPs for DFT, FFT, LTE_FFT

New thread started 2 years ago
Just started looking into Xilinx Fourier transform ip and found out that there are three versions:DFT: apparently useful for any resolutionFFT: power of 2 resolution,...
A current active contract role for an FPGA engineer  is around but sounds very strange in that it tries to explain the FPGA more than the required skills for the...

Re: FPGA perspective of pins versus PCB perspective

Reply posted 2 years ago (02/19/2018)
Thanks vpsampath. That is useful overview indeed.The issue is a common job interview question and I have already compiled my own list but not that sure as I am not...
Hi All,I am looking for any hints on  FPGA pin constraints and their PCB perspective.Are there any established rules for both designers (FPGA & PCB) to work...

Re: Ideas for simple bitrate regulation

Reply posted 2 years ago (02/07/2018)
I am not clear about your issue. Is your clock jittery or are you not sure how to control rate after channel coder. Have you considered clock enable?

Re: If FPGAs didn't work we won't be here?

Reply posted 2 years ago (12/31/2017)
Thanks Adam for the contribution and the links, I will look into them. You confirmed that mitigation is not as easy as just putting back one or so register that...

If FPGAs didn't work we won't be here?

New thread started 2 years ago
Being over-careful  is good practice especially for presentation to the management but factual issues should not be distorted for that sake.What I mean if an FPGA...

Re: Timing constraints priority

Reply posted 2 years ago (11/29/2017)
I found some information from "Vivado Design Suite User Guide Using Constraints" It says:****************"The set_max_delay command can also be used to constrain...

Timing constraints priority

New thread started 2 years ago
Hi All,I am trying to understand an issue with synopsis timing constraints priority (TimeQuest in fact). Suppose I set clock group command to say clk1 is unrelated...

Re: Reduce Phase of a filtered data set

Reply posted 2 years ago (08/31/2017)
filtfilt doubles delay(&more) in physical sense but keeps phase for modelling in software. I don't know any other use of it.Any signal is delayed through a filter....

Re: Mealy or Moore? none and not even state machine

Reply posted 3 years ago (10/07/2016)
indeed. But it avoids talking about state type declaration(present and next if you prefer), state encoding and the hot topic of how many processes needed etc. To...

Re: Mealy or Moore? none and not even state machine

Reply posted 3 years ago (09/30/2016)
I meant counter in any order and not just incrementing, so each count value decides next count value, (not exactly counter but just a set of registers)Kaz
I used to work in the old days of digital design and was familiar with Moore and Mealy style of state machine methodology. It was an attractive University topic...

fft combinations

New thread started 3 years ago
Hi all,I got an FPGA design running #FFT at 256 points. Our system requires fft be configured as either 256 or 512 points on the run. I can use variable fft that...

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