kaz - (@kaz)
set fft_config_data to X"FF09" for 512, for others see user guide then apply this process process(clk) begin if rising_edge(clk) then ...
This has nothing to do with clock transfer. It is about sample rate conversion. A polyphase structure can do that on one system clock. You don't necessarily need...
Use the pin header 2x13This provides 8 input pins, one per channel wired directly to ADC input pins.The DIN value then selects which channel gets converted.
The ADC you have is ADC128S022, 8-Channel, 12-bit A/D Converter, SPI interface.You drive DIN serially on sclk by value, say 000 for ch0 input. Then ch0 DOUT is...
Trying to solve the following contradiction about "set_multicycle_path"case 1: "Vivado using constraints" pdf states that for most cases of timing relaxing multicycle...
Thanks Peter,That is ok for localising bottlenecks but I am really seeing widespread violations as our clock is 491.52MHz with a ZU29 well packed (vivado). I am...
We have plenty data sheets, documents, forum replies and videos on various fpgas and designs. However what is missing in all cases is some idea how fast can one...
Hard to get details of your add-multThere are ways to reduce any filter:Either using LUT if input levels are few and fixed e.g. QAM. so mult results can be precomputed...
If you mean fsysclock is the fpga sampling clock and that it is related to DDS clock then that is ok for clock speed but you still need the input to be synchronous...
The question should be: can the fpga input DROVER be asynchronous? I doubt it since it could be as short as one clock period of DDS yet needs to be seen by fpga....
Thanks,Just pointing out that your video about manual dsp based design is intuitive for study and beginners. some minor issues with pre-adder: it increases data...
Thanks for the video.It is good corner you pointed at. In the 2010s I used DSPBuilder for various FIR filters (single or multirate) and noticed that in many occasions...
I answered you previously but you didn't seem to grasp my view.The SNR equation you refer to is that of quantisation noise (SNRQ) and as measured using full scale...
If you want full use of processing gain then do that at CIC stage. In this case you need to get 17 bits out of CIC and maintain that to FIR and after.To get 17 bits...
I will suggest this:Pass 12 bits data through cic and target 12 bits final output with input/output power unity as a starting point. In the same way treat fir as...
You got plenty of replies, I will add these notes:Your above code drives clock for simulation (testbench). In the device the clock is driven on clock pin which...
The data base terminology in your link directly maps to fpga, the terminology becomes:keys = inputs to your designhash function: logic for mapping those inputs...
I am afraid I can't help with specific lattice environment. However I believe Lattice follows .sdc (synopsis design constraints) file.You can try at least define...
Hi,Here are my initial thoughts1) You can precompute your chosen CDF and insert it in a look up table. This will reduce a lot of run time computations.2) You then...
Hi,The main principle of timing constraints are:1) tell the tool what is your base clock(s) frequency i.e. those clocks that enter from fpga pins rather than any...
I have already indicated those timing paths. What I am questioning is the behavior of the tool itself. Vivado timing does not report warning of unconstrained paths...
Hi All,I 've come across this case (please see figure below) .I have a synchronous system but four constants (A,B,C,D) are implemented on wires and any one of them...
what you described using counters is clock division and is common practice.Your counter may be too wide (23 bits I guess) and thus fails timing on 133MHz clock....
you got setup timing violations (not exactly clock spec issue). I also notice you have gated the clock down to very low speed. My feeling is that your design is...
I suggest you use one clocked process for FSM or you might as well just use a counter instead of explicit state machine. include all assignment in the clocked process...
Now I see your flag signal is not in clocked process so my first post needs correction but I see you have combinatorial feedback on R1
Yes nothing happens until some input arrives to kick start states or counters...etc. You don't have to release activity immediately just because reset is released....
When state changes immediately on reset release then we are doing work. What I mean by "not doing anything at start" is that literally we don't... such that the...
You will need full debugging on all inputs/outputs from ADC to mixer to filter to observation tool. Otherwise it is all guess work. Pulsating waveform could be generated...
Thanks but again I am not asking about basic textbook definitions and micro details.I am simply asking this "Does it matter if a design is not doing anything at...
Hi Adamt99,Thanks for the reply but if the design does not do anything at start so how metastability could occur if no signal is transitioning. Then if it does occur...
Hi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...
I see your point valid. I don't have the answer. One might say the latch edge is either enabled or not but this doesn't explain it since enable is not mandatory...
I follow the LTE standards for radio to ethernet packets. I Don't have choices here.Anyway It turned out that documented table is ok for positive range. For negative...
I did first convert negative values to unsigned(though that is not stated in the doc) then all negative values were opposite in trend. So I removed the conversion...
Hi Josy,Thanks for the reply. I haven't access to code right now but I shifted the 13 bits table towards MSB then kept the same pattern. for example the lowest table...
Hi all,Referring to this doc on A law compression (table 1):http://www.young-engineering.com/docs/YoungEnginee...The table is meant for 13 bits signed to 8 bits...
Thanks for that Martin but I noticed the same option for 1536 is available with fft ip setup.Moreover I assume they could have done one ip for DFT and fft and lte...
Just started looking into Xilinx Fourier transform ip and found out that there are three versions:DFT: apparently useful for any resolutionFFT: power of 2 resolution,...
Thanks vpsampath. That is useful overview indeed.The issue is a common job interview question and I have already compiled my own list but not that sure as I am not...
Hi All,I am looking for any hints on FPGA pin constraints and their PCB perspective.Are there any established rules for both designers (FPGA & PCB) to work...
I am not clear about your issue. Is your clock jittery or are you not sure how to control rate after channel coder. Have you considered clock enable?
Thanks Adam for the contribution and the links, I will look into them. You confirmed that mitigation is not as easy as just putting back one or so register that...
Being over-careful is good practice especially for presentation to the management but factual issues should not be distorted for that sake.What I mean if an FPGA...
I found some information from "Vivado Design Suite
User Guide
Using Constraints" It says:****************"The set_max_delay command can also be used to constrain...
Hi All,I am trying to understand an issue with synopsis timing constraints priority (TimeQuest in fact). Suppose I set clock group command to say clk1 is unrelated...
filtfilt doubles delay(&more) in physical sense but keeps phase for modelling in software. I don't know any other use of it.Any signal is delayed through a filter....
indeed. But it avoids talking about state type declaration(present and next if you prefer), state encoding and the hot topic of how many processes needed etc. To...
I meant counter in any order and not just incrementing, so each count value decides next count value, (not exactly counter but just a set of registers)Kaz
I used to work in the old days of digital design and was familiar with Moore and Mealy style of state machine methodology. It was an attractive University topic...
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