Christopher Felton (@cfelton)

Christopher Felton building DSP digital circuits with MyHDL.

Summer of gateware is coming (again)

Christopher Felton April 29, 20162 comments

How time flies!  I swear my last post was a summary of the 2015 summer of gateware.  This year (2016) MyHDL is participating in the Google summer of code again, for the second year, continuing as a sub-org of the Python Software Foundation organization.

This year, so far, has been amazing and inspiring.  We have had many talented students inquire about the project and contribute to myhdl and

Summer of Gateware

Christopher Felton September 18, 2015

This (last) summer the MyHDL project participated in the Google Summer of Code (GSoC) as a sub-organization under the Python Software Foundation (PSF). This was our first year participating - there was a lot for us to learn.  Overall it was a worthwhile and beneficial activity.

Being a first time sub-org we were limited to a maximum of two students.  We had nine students apply and twelve mentors volunteer.  Only being able to select two students...

I don’t often convert VHDL to Verilog but when I do ...

Christopher Felton December 24, 20142 comments
VHDL to Verilog

I don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement).  For the most part I am HDL agnostic.  Well that is not true, I have a strong preference for MyHDL, and an insubstantial preference for VHDL over Verilog.  The choice of HDL for a project is often complicated, irrational, sometimes rational, but most often random.  It is often not a choice of the developer - for...

Point of View

Christopher Felton August 28, 20146 comments

I was caught of guard when someone commented:

"when a FIR filter is full of multiple loops and complex code, something is wrong"

The comment was made during an informal discussion on alternative hardware description languages (HDL) and was targeted to the straightforward FIR filter implemented in MyHDL

(different FIR description simulation results) 

Personally, (and...

MyHDL Presentation Examples

Christopher Felton August 26, 2014

The last two years I presented at EELive.  The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper].  The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL.  I also presented at a regional Python conferene: pyohio.  At the Python conference I presented...

[Comments] C HLS Benefits

Christopher Felton April 11, 20142 comments

Earlier this week I posted a small write-up comparing a hardware median calculation implemented in a C-to gates "HLS" (Vivado C HLS) and a version in MyHDL.  For a long time I have had the belief that C-to-gate technologies are of little to no benefit - based on the simple premise that "C" is not that high-level of a language (I actually consider it lower than Verilog and VHDL ... but that is a conversation for another time).

Language comparisons...

Little to no benefit from C based HLS

Christopher Felton April 4, 2014

Last updated 07-Nov-2015

As I write this I am on a plane and my destination is EELive 2014 where I am going to give a talk hardware design: the grunge era.  It is a shotgun introduction to three alternative hardware description languages (alt.hdl). The three languages briefly introduced in the talk are: bsv, chisel, and myhdl.  The goal of the talk is simply to raise awareness of the three...

MyHDL Interface Example

Christopher Felton January 18, 20142 comments
MyHDL Interfaces Example

With the next release of MyHDL, version 0.9, conversion of interfaces will be supported.  In this context an interface is any object with a Signal attribute.  This can be used to simplify connection between modules and port definitions.  For example, if I want to define a simple memory-map bus, the Signals for the bus can be defined as follows:

class BareBoneBus: def __init__(self): self.wr = Signal(False) self.rd =...

MyHDL @EDAPlayground

Christopher Felton October 24, 2013

Trying out MyHDL became a little easier recently.  MyHDL is now avaialbe @EDAPlayground.  One can experiment with Python/MyHDL verification of HDL modules and implementing complex digital cirucits in MyHDL.

The @EDAPlayground has two main panels. On the left is the testbench and the right the HDL description to be tested.

There are a couple examples...

binary hello world

Christopher Felton August 3, 20132 comments
Python + Ohio + MyHDL + FPGA

Recently I had the opportunity to coordinate a hands-on programmable hardware (FPGA) workshop (open-space) at a regional Python conference - @pyohio. The workshop was for those that had little to no exposure to programmable hardware. For this situation I used two basic examples: two versions of a binary hello world.

The binary hello world -- blinking an LED -- is a good starting point to introduce programmable hardware, hardware descriptions languages,...

Tool install for examples

Christopher Felton August 2, 20132 comments

Most of my examples on fpgarelated use MyHDL for the hardware description and another Python package myhdl_tools rhea.build to control the FPGA vendor's software. This means everything is controlled and run from the Python environment.

Install the following to compile the posted examples:

MyHDL package : pip myhdl or myhdl github myhdl_tools : myhdl_tools bitbucket rhea...

What do Ohio, Python, and FPGAs have in common?

Christopher Felton July 23, 2013

Anyone in the Columbus Ohio area in the United States this upcoming weekend (7/27 and 7/28) should stop by the @pyohio conference.  This is a *FREE* regional python conference.  I will be giving a talk at the end of the day Sunday, discussing MyHDL, FPGAs, and a hands-on workshop following the presentation.

The talk will focus on introducing programmable hardware to "imperative thinkers".  Anyone curious about FPGAs, Python, or familiar with FPGAs or embedded...


Christopher Felton June 3, 20135 comments

The PWM topic appears to be popular lately on the fpgarelated site.  This is coincidence, but I typically find the topic of modulating and demodulating signals interesting.  For digital systems it is always entertaining to play with PWMs.  The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin.  The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).  


MyHDL Resources and Projects

Christopher Felton December 9, 20122 comments

Last updated 07-Nov-2017

MyHDL Resources

If you want to dive into MyHDL (digital hardware description in Python) there are many resources available.  Below is a list of MyHDL resources, including some of the past blogs here on fpgarelated.

The MyHDL manual is a great (probably the best) place to get started.

The manual is an in-depth introduction to MyHDL.  The concepts are well explained and there are examples to test while working through the...

MyHDL FPGA Tutorial II cont. (Echo, Audio Interface)

Christopher Felton September 13, 201210 comments

To demonstrate the echo on an FPGA board an interface to an audio ADC/DAC chip will be used. The following will explain the connection to the audio codec and the HDL module used to interface.

Audio Codec Interface

I have two boards with TI AIC23b audio codecs. The AIC23 has a configuration interface (ability to program the registers) and a streaming audio interface. The SPI mode will be used to configure the codec and the I2S interface is used to send and...

MyHDL FPGA Tutorial II (Audio Echo)

Christopher Felton July 18, 2012

This tutorial will walk through an audio echo that can be implemented on an FPGA development board.  This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial.  This project will require an FPGA board with an audio codec and the interface logic to the audio codec.

Review the Previous Tutorial

The previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board.  In that tutorial we introduced the basics of a MyHDL module....

Are you kidding me?

Christopher Felton July 1, 2012

If I understand the blog entry [1] correctly, it's saying the industry is ready for high level synthesis (HLS), well almost.  The blog states, the higher abstraction level will be achieved via C/C++/SystemC (the C-centric flows).  A quote from the blog.

... getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- ...

C/C++/SystemC, are you kidding...

Grandiose Delusions

Christopher Felton May 3, 2012

Recently on the MyHDL mailing-list there have been discussions about some other immature Python/HDL tools.  In these discussion it was mentioned, how over the years, there has not been a strong set of open-source IP developed using MyHDL.  For those that might be unfamiliar with the term IP (intellectual property) it is a term widely used in digital hardware to refer to reusable hardware components or blocks.

Many design languages have relied on that first big...

MyHDL FPGA Tutorial I (LED Strobe)

Christopher Felton January 31, 20126 comments

Last updated 05-Nov-2015


From many perspectives the latest FPGA offerings from 'X' and 'A' are large devices - mucho programmable logic resources.  Even the devices that one can get for sub \$10 are relatively large.  Because of the size of these FPGAs they are implemented using an HDL.  To manually configure each circuit would be a long and tedious task.  It is not feasible to program an FPGA by manually defining the logic for each LUT and manually...

USB-FPGA : Introduction

Christopher Felton January 12, 20111 comment

This blog is an introduction to a series of blogs I hope to write.  The blogs will cover the design and experiences I had on a project that spanned the last 6 years.  The project was the development of an USB FPGA board and the supporting gateware, firmware, and software.  The project has had different levels of activity over the years, ranging from none to some, but it has been an ongoing project, albeit, during sleepless nights.  Lately, I have ported the HDL (gateware)...

A Bit Bucket had Holes

Christopher Felton July 28, 20101 comment

Couple months ago I wrote a quick little blog about a company called Tabula.  Tabula has a virtual 3D approach to achieving higher logic density in an FPGA.  See the previous blog for more information.

Along similar lines was another company called TierLogic which actually had multiple physical layers.  I was impressed with the Tabula approach and claims.  Along the same lines the TierLogic technology looked promising as well.  But, EE Times has reported that...

Developing FPGA-DSP IP with Python

Christopher Felton March 16, 20101 comment

This blog post was previously titled MyHDL ASIC Proven (How is this related to FPGAs?) but the blog post has been updated and mainly discusses developing FPGA-DSP IP with Python / MyHDL. The original content is still present but the post has been reorganized and expanded. Original post 16-Mar-2010.

Developing FPGA-DSP IP with Python / MyHDL

Using Python to develop DSP logic for an FPGA is very powerful. The Python ecosystem contains many packages including numerical and...

Holy Bit Bucket

Christopher Felton March 3, 2010

Was my first response after reading some of the recent news on Tabula.  If you Google "Tabula FPGA" you will find a link to the company and a bunch of recent articles.  The company appears to be building buzz (hmmm, wonder if they have facebook and twitter accounts) about their technology and future products.  

There has been some discussions (comp.arch.fpga) and a bunch of small articles about the relatively new FPGA company. The company is trying to increase...

The Spartans

Christopher Felton February 20, 20104 comments

The latest release of the Xilinx Spartan family is the Spartan6 line of FPGAs. It has been awhile since the last major Spartan released, the Spartan3, but this last year Xilinx released the Spartan6. The Xilinx Spartan family is the low cost FPGAs compared to the higher cost and high performance Virtex family. The Spartan family is derived from the Virtex architecture with some changes to reduce the cost. The Spartan3 FPGAs were derived from the Virtex-II architecture. Since the Spartan3...

Re: Synplify Pro for Lattice not working

Reply posted 7 years ago (04/23/2017)
I haven't had issues with Lattice/Syn Pro on my system (don't use roaming profiles) but I have had tons of issues with roaming profiles previously.  I requested...

Re: Synplify Pro for Lattice not working

Reply posted 7 years ago (04/23/2017)

Re: Mealy or Moore? none and not even state machine

Reply posted 8 years ago (10/07/2016)
I imagine many things in life that can be avoided with obfuscation. 

Re: Mealy or Moore? none and not even state machine

Reply posted 8 years ago (09/30/2016)
I don't think it is useful to try and design a Mealy or Moore (more is less) state-machine.  In some limited cases it can be useful for analysis (reviewing...

Re: Use Microblaze performance monitoring engine

Reply posted 8 years ago (04/29/2016)
@adamt99 is the microblaze expert, he might have some input.
@paulkushner, I have been in both situations but regardless if there are resources to write the application code I typically find myself writing the bare minimal...
Paul (@paulkushner),I do not have any direct experience trying to use an MMCM is such away, I don't have an answer to your specific questions.  But I am familiar...
@oliviert The existing landscape of HDL HLS is a misnomer :)   Computer Science: "In low-level languages like C"Computer Engineering: "In high-level languages...
@adamt99 (Adam),I feel most at peace with the Sigasi point of view, the graphical displays are great for viewing the results and a means of debugging.  From my...
@oliviert, thanks for the comments!  Correct, it is not required to use the block-diagram (BD) systems but if you want to use the IP (cores), “they” in many...
This is more of a transmission line and/or PCB issue, you need to make sure the delay on each of those traces is within tight tolerances.  On the lower end of your...
Viewers are great tools and can be very useful in analyzing and debugging. http://www.slideshare.net/sigasi/graphical-program... Might be different strokes for...

Re: Code review. Newbie's first verilog module!

Reply posted 8 years ago (03/24/2016)
This will synthesize with most FPGA tools reg [31:0] count = 0; reg [63:0] dataBitsIN = 64'd0; reg [7:0] bitCount = 0; And is often recommend as the initialization...
Hopefully you feel welcome in this forum :)There could be a couple things going on: first you might be unlucky and are running into the few that need to tear others...
@SpiderKenny I am not familiar with Zeidman's book but it seems odd that any contemporary text book on HDL would think schematic entry is useful.  If one is not...
Both XIlinx and Altera waste copious amount of time and resources creating tools to "help" FPGA system designers.  The issue, in my opinion, is that these tools...

Re: Best method for a large dot vector

Reply posted 8 years ago (03/05/2016)
The OP didn't specify the bits widths in the design.  In general, you will be best off using the hard multipliers in an FPGA.  I would be surprised if this design...

Re: Best method for a large dot vector

Reply posted 8 years ago (03/04/2016)
@garengllc, the code will take a little bit to decode but based on your description implementing 274 point dot product, and given some of the constraints I would...

Re: Best method for a large dot vector

Reply posted 8 years ago (03/04/2016)
@garengllc,  I should clarify, you can break you code down like this: The following is my state-machine and it does XYZ always @(posedge clock) begin // state-machine...

Re: Best method for a large dot vector

Reply posted 8 years ago (03/04/2016)
@garengllc instead of dumping your complete code in the post, it is probably best to isolate a snippet of the code (digestable in the post) and then link to the...

Re: FPGA size and tools

Reply posted 8 years ago (02/23/2016)
My experience has been in the opposite direction.  The latest industry tools are lacking considerably to build large complex systems.  As you outlined, the tools...
At some point in the past I had used a carry-select-adder to meet timing for a larger adder.  I did a little experiment to see how often this is true.  The following...

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