Hardware Design Engineer, specialized in FPGA/ASIC, working on a startup, currently in Bangalore

Re: How to make sure clock is from the main clock tree?

Reply posted 5 months ago (05/07/2020)
Every clock has a source. The clock input(s) to the FPGA would be used to generate the clock required by the circuit. The synthesis and the tools downstream trace...

Re: Is this possible with an FPGA?

Reply posted 7 months ago (03/20/2020)
Joe,You have to know the hall sensor characteristics. If the output is analogue which is most likely, you have to deal with a digital number along with phase relationship....

Re: Is this possible with an FPGA?

Reply posted 7 months ago (03/19/2020)
...

Re: Timing paths from wires to registers

Reply posted 11 months ago (11/10/2019)
STA does consider arrival time and wired delay of signal inputs. In this case arrival time is 0 and these are not primary inputs. Only wire delay is considered...

Re: Timing paths from wires to registers

Reply posted 11 months ago (11/07/2019)
There are timing paths from 2 sides, the input to output and constants to output, and up to D input of the final register is a combo block. The source of multiplicand...

Re: FT601Q: 245 Synchronous FIFO mode.

Reply posted 1 year ago (09/03/2019)
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Re: Use of DAC in ZCU111 Dev Board

Reply posted 1 year ago (08/13/2019)
There are different ways a square wave could be implemented using FPGA.       From your mail it seems you are interested in using the RF DAC built in the FPGA....
UCF is the pre-VIvado style of specifying constraint for Xilinx FPGA tools. XDC is the format similar to Synopsys design constraints used with Vivado tools. Please...

Re: Reusing registers in VHDL FSM code

Reply posted 1 year ago (07/04/2019)
To change state after the ALU operation you donot need flag. You could just change state and still assign flag so you know which operations completed. Also you could...

Re: Tips for using Xilinx Ultra RAMs

Reply posted 1 year ago (06/20/2019)
Ultraram is in ram only mode and no fifo mode available. Single clock (not an asynchronous memory) 2 ports but not a true dual port. Synthesis infers ultra ram....
Recovery time - Min time required from reset release TO active clock edge. Removal time - Min time required from active clock edge TO reset release. In the case...

Re: register clear on read

Reply posted 1 year ago (06/08/2019)
When read signal is active register is reset to "0" and read_bus <= register_val. Status registers, interrupt registers, statistics counters are implemented this...

Re: metastabilty with multicycle

Reply posted 1 year ago (05/18/2019)
Metastability occurs when signals cross clock domains as uncertainty is not known. Metastability exists (it is a probability) even if domains were to be on-chip...

Re: fpga spartan 6 io ports are no longer working

Reply posted 1 year ago (05/05/2019)
Please Check in the schematic if all VDDs and GNDs are connected to appropriate levels for the particular part - Core voltage, Auxiliary voltage, IO voltage etc.. Then...

Re: Code

Reply posted 2 years ago (04/05/2019)
The loop is rolled out 4 times to generate a concatenated vector. I assume s0o.. are all 8 bit wide.

Re: Mixed columns for AES algorithm

Reply posted 2 years ago (03/21/2019)
A much simpler alternative could be that your new algorithm be developed in C/C++ and validated in a C/C++ suite. Later the same could be ported to FPGA using...
Any recommendation could get too long for a forum discussion. However an itemized recommendation to get a start is possible.1. If you are new to Verilog, you would...

Re: Suggest a FPGA project

Reply posted 2 years ago (01/08/2019)
Well VII Pro is more than a decade old, but back then people have implemented sophisticated logic with it. The current trend is in AI. Deep learning, regular learning,...
For simplicity consider a DVI Quad Link which has 12 channel Synchronous streams with a 120 bit interface and clock. It is possible to encapsulate the pixel and...

Re: replacement for XILINX XC3020A-7PC84C

Reply posted 2 years ago (12/01/2018)
From your description I am sure you would have already gone through Xilinx product line. As Technology nodes change 5V IO is not being supported. Obviously some...

Re: Learning FPGA

Reply posted 2 years ago (09/13/2018)
Alright, We are in the age of 16nM FPGAs, thinking of 7nm, 3nM .., DDR5, Network on chip, Multi GHz cpu cores, Image processing, DSPs, IoT, Cloud and so on, Employers...

Re: remains a black box sine it has not binding entity

Reply posted 2 years ago (08/29/2018)
This is the message by builder. You may want to look at Synthesis report and look for warnings. Code seems mixed up with state assignments and output assignments,...

Re: remains a black box sine it has not binding entity

Reply posted 2 years ago (08/27/2018)
I assume i2c_master_src is complete.If the whole module is optimised out by the tool there is a chance of missing entity. If possible could you share the messages...

Re: Lattice: Utilization and Clock Report

Reply posted 2 years ago (07/26/2018)
Clock load is a physical quantity, and is different from the number of registers but depends on the path. There could be fewer sequential elements but depending...

Re: BRAM based FIFO

Reply posted 2 years ago (07/06/2018)
The above code would infer a memory (BRAM if you are targeting Xilinx) with write and read logic but NOT a FIFO. If you need a FIFO in the design, a FIFO could be...

Re: Searching for info about very old FPGA devices

Reply posted 2 years ago (05/28/2018)
I found mention of Plus logic in the bibliography section of the book "Field Programmable Gate Arrays" by Stephen brown et al. This means they would have referred...

Re: Mux versus internal high impledance

Reply posted 2 years ago (05/06/2018)
In a tri-state the totem pole output transistors are not driven meaning they are off. If such a structure could be inferred from an HDL model then we are sure that tri-state...

Re: Mux versus internal high impledance

Reply posted 2 years ago (05/04/2018)
Either ASIC/FPGA, Tristate is not permitted within the fabric. The only place to implement tristate are the IOs. Parameterisation is a matter of coding style, does...

Re: Writing 16-bit data to bram

Reply posted 2 years ago (04/26/2018)
In C the short data type is usually 16 bits. In the above code it seems it is 32 bits. May be addr could be declared as int.

Re: Best FPGA for Harvard Architecture

Reply posted 3 years ago (04/03/2018)
A plug in type SRAM architecture may not be available. Try ML561. You could additionally search for "Xilinx evaluation board with SRAM" on google.
I was told by a Avnet support engineer that ISE 14.7 works best on Windows 7 32 bit. I had similar issues with later versions of ISE 14.7 and switched to WIndows7...
When we talk about FPGA and its applications in Embedded Systems, we must consider 2 aspects 1. FPGA visa vis Software 2. FPGA visa vis traditional ASICs. FPGA has...

Re: 1st project having issues with latches?

Reply posted 3 years ago (09/13/2017)
Hi @Coryset,The MC14514 data sheet is available from ON Semi : https://www.onsemi.com/pub/Collateral/MC14514B-D.P...The select input is strobed and stored by transparent...

Re: Effective schematic for GPIO pin

Reply posted 3 years ago (05/26/2017)
1. FPGA output driving gate of MOSFET ? It would be wise to use a speciality MOSFET driver and drive the inputs of the driver from FPGA GPIO. FPGA GPIO need not...

Re: Guidelines for porting ASIC RTL to FPGA

Reply posted 4 years ago (04/04/2017)
I assume you have designed ASIC.1. Memory blocks - In ASIC behavioral models have to be replaced by blocks created using Memory compiler. Decide upon Block/Distributed...

Re: Synchronizing Multiple FPGA Prototype Boards

Reply posted 4 years ago (03/07/2017)
To state the problem in simpler words, There are 4 masters, Each master needs a clock to control 64 IO lines, BUT all 4 clocks must be in SYNC (may be same phase)....

Re: sampling 800mbps data in virtex 5QV

Reply posted 4 years ago (03/01/2017)
760MHz - Do you mean sample rate ? Some converters (-45 to 85 Degree C) use standardized serial interfaces providing BW from ~300Mbps to 3+ Gbps. RocketIO/MGT is...

Re: Simple logic

Reply posted 4 years ago (12/28/2016)
Problem is expressed in the form of truth table below. Note output persists at LOW after driven LOW by S2 until the next rising edge of S1 at which time S2 should...

Re: APB Bridge

Reply posted 4 years ago (12/21/2016)
Please take a look at the state diagram in the APB spec, Write/Read transfers and related interfaces and timing diagrams. You would get ideas of your own to implement...

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