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Juergen Schuhmacher (@engineer68)

Electric engineer involved in digital signal processing for medical and military.

Re: Implementing a folded FIR on FPGA

Reply posted 1 year ago (02/16/2023)
Show me a working core where statistical and optimized truncation by rounding is performed automatically (and correctly) while calculating the physical constraints...

Re: Xilinx FIR Compiler Fractional Rate Converter

Reply posted 1 year ago (02/16/2023)
I do not think there is an issue with the conversion itself. I only mentioned this as a side aspect.As stated the unexpected gaps are the issue.The question is,...
Did you connect the signals correctly? There is no reason to GND anything in this case. In the opposite, the PINs should be used as outs only, according to my understanding.One...
I think it is because it is a signed MUL and may exceed the limit of one DSP.

Re: LVDS as a comparator

Reply posted 1 year ago (02/16/2023)
There are actually two methods in doing this:A self running oscillator adding noise onto the signal causing statistical toggling, which is (over-)sampled, reduced...

Re: Is this possible with an FPGA?

Reply posted 1 year ago (02/16/2023)
Although most has been alread said to that, one add of mine:Hall Sensors and others require noise processing and leveling in order to be easily processed with a...

Re: Lattice FPGA timing constraint help

Reply posted 1 year ago (02/16/2023)
Question regarding this: I also dealed with the ULTRAPLUS recently and found it difficult to follow this particular design flow since there seemed to be more than...

Re: Aldec Active-HDL vs Modelsim PE state of play.

Reply posted 1 year ago (02/16/2023)
The fun fact I recently discovered with XSIM, that Xilinx did not recomend to use it together with a simulation where an UltraScale HBM was involved and pointed...

Re: Xilinx FIR Compiler Fractional Rate Converter

Reply posted 1 year ago (02/16/2023)
I am having a problem in understanding the decimation ratio of 128:125 and "link" it to your frequencies: Where is the asynchronous point about that?Typically this...

Re: Implementing a folded FIR on FPGA

Reply posted 1 year ago (02/16/2023)
"In actual industry we use ip core for filter and forget about manual design as it is quicker."You certainly mean "designing the filter is done more quickly".Well,...

Re: RC-filter in VHDL

Reply posted 1 year ago (02/16/2023)
Optimize simulation or optimize real calculation and resource usage?COS(x) can be calculated in real time or be approximated with polynomic equations if there is...

Re: FPGA speed and timing closure metrics

Reply posted 1 year ago (02/16/2023)
I agree when it comes to the summed up violation value. The next figure will be the sum of all slacks in the department and then in whole country. I wonder what...

Re: FPGA for audio DSP

Reply posted 1 year ago (02/16/2023)
> " But it would be better to filter the signals which are quantized by the frequency higher than tenths of MHz."or use the FPGA power to process more than one...

Re: FPGA for audio DSP

Reply posted 1 year ago (02/16/2023)
I would suggest that an MCU / audio DSP chip is the best solution for this, since these usually already provide the necessary interfaces nowadays. FPGAs should only...

Re: FPGA - how to receive and use external trigger

Reply posted 1 year ago (02/16/2023)
I suggest you are using the COM-Interface lines in the VGA / CL - lane?If not, triggers usually are best kept as a forbidden character or a key embedded in the data...

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