Aldec Active-HDL vs Modelsim PE state of play.

Started by glenenglish 1 year ago2 replieslatest reply 1 year ago81 views

What's the state of play here  in 2021 ? I have had a Modelsim PE seat in maintenance for 16 years. Modelsim has not changed, improved any done anything in that time. Zippo. nothing. The dual language upgrade cost for Modelsim  is about USD$10k , insane !!! then extra 500/year which is probably OK.

I only stay in Modelsim Maintenance because Xilinx keep changing compressed and encrypted file formats for IP  which when modelsim gets a couple of years old  it will not recognize the Xilinx changes..

I only do VHDL simulation to waveform all from my own scripts.... test-benches etc, I do no post place-and-route simulation, no need for source code step and debugging.... The is a coming need for Verilog though, alot of the  XIlinx IP is moving to  Verilog only , so far I have just not used them and written my own IP to get around my lack of ability to simulate Xilinx IP written in Verilog.. 


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Reply by StephenrfarmerMay 28, 2021

I've used Modelsim, Active HDL and Xilinx Vivado XSIM.

I have a version of Modelsim available at work but I still prefer XSIM because it's free and has most if the features I could ever want.

My simulations are fairly complex. They are self checking, written in Systemverilog (it supports all the HDL's), post-synth, some randomization and class based. It also supports UVM which I haven't used yet. The only things it lacks so far is ability to view VHDL variables and code coverage. Although it supports functional coverage.


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Reply by glenenglishMay 30, 2021

thanks for the advice

I found Xsim slow compared to Modelsim PE. I dont need anything fancy, just plain old VHDL, verilog and waveforms...

Looking closely at ActiveHDL now. 

thanks again.