Summer of Gateware

Christopher Felton September 18, 2015

This (last) summer the MyHDL project participated in the Google Summer of Code (GSoC) as a sub-organization under the Python Software Foundation (PSF). This was our first year participating - there was a lot for us to learn.  Overall it was a worthwhile and beneficial activity.

Being a first time sub-org we were limited to a maximum of two students.  We had nine students apply and twelve mentors volunteer.  Only being able to select two students...


Homebrew CPUs: Color Languages

Victor Yurkovsky June 18, 2015
Color Languages

Here on bizarro we program using -- get this – text!  Our other senses - hearing, touch, smell, are not used at all. Even our visual perception is greatly underutilized - we just use two-dimensional text on a flat display a foot in front of our eyes.

Color is just beginning to be used, although in a lame syntax coloring way only. Granted, it makes it easier to detect stupid syntax errors such as misspelled keywords. Sadly, color carries zero semantic or...


PC and SP for a small CPU

Victor Yurkovsky July 23, 2013

Ok, let's make a small stack-based CPU.

I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.

Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...


StrangeCPU #4. Microcode

Victor Yurkovsky May 13, 20137 comments
Summary:

Sliding windows containing runs of microcode.

Table of Contents:

StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!

Victor Yurkovsky March 18, 201311 comments
Summary:

Decoding instructions with a Sliding Window system.  0-Bit Sliding Register Windows.

Table of Contents:

StrangeCPU #2. Sliding Window Token Machines

Victor Yurkovsky March 5, 201313 comments
Summary:

An in-depth exploration of Sliding Window Token Machines; ARM notes.

Table of Contents:

StrangeCPU #1. A new CPU

Victor Yurkovsky February 25, 20136 comments

Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even 64-bit address space, using not much more than an adder.

Table of Contents:
  • Part 1: A new CPU - technology review, re-examination of the premises;  StrangeCPU concepts; x86 notes.

Verilog vs VHDL

Muhammad Yasir June 13, 2011

Introduction

 

Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...


StrangeCPU #1. A new CPU

Victor Yurkovsky February 25, 20136 comments

Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even 64-bit address space, using not much more than an adder.

Table of Contents:
  • Part 1: A new CPU - technology review, re-examination of the premises;  StrangeCPU concepts; x86 notes.

StrangeCPU #2. Sliding Window Token Machines

Victor Yurkovsky March 5, 201313 comments
Summary:

An in-depth exploration of Sliding Window Token Machines; ARM notes.

Table of Contents:

StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!

Victor Yurkovsky March 18, 201311 comments
Summary:

Decoding instructions with a Sliding Window system.  0-Bit Sliding Register Windows.

Table of Contents:

Verilog vs VHDL

Muhammad Yasir June 13, 2011

Introduction

 

Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...


PC and SP for a small CPU

Victor Yurkovsky July 23, 2013

Ok, let's make a small stack-based CPU.

I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.

Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...


StrangeCPU #4. Microcode

Victor Yurkovsky May 13, 20137 comments
Summary:

Sliding windows containing runs of microcode.

Table of Contents:

Homebrew CPUs: Color Languages

Victor Yurkovsky June 18, 2015
Color Languages

Here on bizarro we program using -- get this – text!  Our other senses - hearing, touch, smell, are not used at all. Even our visual perception is greatly underutilized - we just use two-dimensional text on a flat display a foot in front of our eyes.

Color is just beginning to be used, although in a lame syntax coloring way only. Granted, it makes it easier to detect stupid syntax errors such as misspelled keywords. Sadly, color carries zero semantic or...


Summer of Gateware

Christopher Felton September 18, 2015

This (last) summer the MyHDL project participated in the Google Summer of Code (GSoC) as a sub-organization under the Python Software Foundation (PSF). This was our first year participating - there was a lot for us to learn.  Overall it was a worthwhile and beneficial activity.

Being a first time sub-org we were limited to a maximum of two students.  We had nine students apply and twelve mentors volunteer.  Only being able to select two students...