I am looking for any hints on FPGA pin constraints and their PCB perspective.
Are there any established rules for both designers (FPGA & PCB) to work in harmony.
Once you understand the main FPGA interfaces and have created a mockup of the physical layout, you can start to define the pinout. Some designers like to use a spreadsheet containing all of the I/O signals to keep track of the pins. You can group them by voltage, by clocks, by interface, or by bus. This method is really quite valuable because it helps you begin to formulate the groups of signals you will assign in close proximity. At this stage, you should also identify critical interfaces that must exit the device on a particular edge or use outside physical pins for optimal PCB routing.
After examining both the FPGA and PCB requirements and defining the major interface locations, the next step is to begin assigning pins to I/O banks based on all of the preceding criteria. This is where the real work begins. In the current flow, pin assignment is a time-consuming task that can involve a lot of trial and error to solve any performance and signal integrity concerns. Designers have traditionally performed this task freehand, because EDA and chip vendors didn't offer tools to effectively help designers visualize the two domains.
Rather than go into detail about every feature of the tool, let's see how we can use it in the context of an I/O pin assignment methodology
Thanks vpsampath. That is useful overview indeed.
The issue is a common job interview question and I have already compiled my own list but not that sure as I am not PCB designer. I am posting them here just to stimulate this discussion and share with the forum if any issue is missing or irrelevant:
(1) Early co-development between FPGA and PCB for the sake of fpga timing closure, including iterations.
(2) FPGA rules such as io banks issues, ref voltages, terminations for impedance matching, dedicated pins must be identified.
(3) Make use of unused pins for changes or future additions
(4) Fast signals to be identified (trace width & spacing & layers)
and specially fast/high fanout clocks to be identified to minimise jitter, duty cycle issues...etc.
(5) Special interfaces that must be on a specific side of fpga have to be identified