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metastabilty with multicycle

Started by nori 3 months ago3 replieslatest reply 3 months ago40 views

Hi All,

This thought occurred to me regarding multicycle path.

Assume I set multicycle of 2. Then this implies that data delay from launch edge(0) will respect the timing at latch edge(2). while edge(1) will not be respected and could well be violated. So how come metastability isn't an issue and no two stage synchronisers are needed. I know latch edge(2) will sample without violation but the events at edge(1) aren't absorbed just like any asynchronous case.

Regards

Nori


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Reply by kazMay 18, 2019

I see your point valid. I don't have the answer. One might say the latch edge is either enabled or not but this doesn't explain it since enable is not mandatory for multicycle.

I know multicycle works without problem if applied correctly so it could be this issue of metastability is questionable and a register will do its job as long as its sampling edge is not violated. Or it could be that clock enable is indeed needed for multicycle path.

Another thought is that the case of multicycle violation is different from case of clock crossing. With clock crossing any output sampled could go metastable but with multicycle the violated edge is not relevant as the next edge comes and samples input correctly overriding previous edge violation. 

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Reply by jsanchezMay 18, 2019
Only one cycle is needed because meta-stability is resolved before the next cycle (this process is random, with very low probability to pass the second register).  There is a formula that calculates the time that exists for the probability to occur in the second register, this value at normal working frequencies is usually greater than 100 years.


You have a good explication in http://www-classes.usc.edu/engr/ee-s/552/coursematerials/ee552-G1.pdf

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Reply by rajkeerthy18May 18, 2019

Metastability occurs when signals cross clock domains as uncertainty is not known. Metastability exists (it is a probability) even if domains were to be on-chip whether in ASIC of FPGA(though here clock paths are already laid). Setting higher values of multicycle would not resolve metastability as uncertainty is still unknown between domains. Multicycle is relevant only in the same clock domain!!

To resolve metastability synchronizer is required. One must consider clocking domains being crossed i.e., slow-to-fast, fast-to-slow and clock frequency in the same range. Sometimes a string of flops may not be right and handshake would be required and it is a design issue. In the same domain metastability would not occur since clock tree is balanced and uncertainty is known.