I followed carefully the 2:1 MIPI CSI-2 Bridge Soft IP User Guide which suggest the usage of clarity designed. I configured the IP in left right (one line, 2 MIPI flows as Rx and one MIPI flow as output) mode and chosse Synplify Pro for synthesis.
What I observe is that, after importing the IP in the design (the sbx and the ldf generated by clarity designer) just the Rx input are assigned and exposed to IO pads as MIPI buffers, while the Tx output are not assigned to IO pads at all (neither as MIPI buffers nor other types of IOs). In the example LDF file I cannot dind in fact IO pads assingnment (and either timing and IO constraints: is this normal for an IP???)
How can I make this working, i.e. expose Tx MIPI to IO pads? and also change their position to stick the pad to the customer board (they designed the board against the lattice evaluation borad assuming the FPGA generation pinn assignment was the same).