Forums

Max IO speed for capturing Source Sync Data into an FPGA

Started by john earls 5 years ago3 replieslatest reply 5 years ago99 views

Hi - I'm looking into capturing data into an FPGA from a device that can supply either 80 or 160 bit wide data with a source sync clock.  The data rate can be anywhere from 100MHz to 800MHz.    I'm trying to figure out how fast I can capture data, taking into account skew over the data bus, and distribution of the source sync clock.

I'm currently using an older 28nm device, but on the next spin I can switch to the latest FPGA (either X or A).

Thanks

John

[ - ]
Reply by adamt99April 21, 2016

cfelton is correct this is definitely a layout issue, having done some high speed parallel buses at near the speeds you mention you will carefully need to consider not only the termination as mentioned but also the following

1) are these single ended or differential - if possible use a differential standard I would assume differential is the only way to go at these speeds. 

2) you need to ensure the characteristic impedance of the tracking is controlled as required - 50 Ohm or 100 ohm are typical depending upon the technology 

3) be careful of track skew can you group them up (you have a wide bus I think) such that the layout routing can be easier (it will still be demanding but why make it more than it has to be) 

4) be sure to take into account the Jitter 

5) at these speeds you will need to ensure you have a good set of routing rules for the layout engineer. especially regarding how close tracks come to each other for crosstalk reasons and how close they can come to any sensitive signals

Hope this helps 

Adam 

[ - ]
Reply by cfeltonMarch 31, 2016

This is more of a transmission line and/or PCB issue, you need to make sure the delay on each of those traces is within tight tolerances.  On the lower end of your range you could probably get it to work on the upper range it will be more difficult. 

With some careful massaging you might be able to get the FPGA to compensate (add delay) to each line to get them to line-up but it will be tricky, I have not attempted such a problem at your upper requirements.

You will need to do some careful analysis to determine the max rate for your system but my guess you would be limited to you lower end of the range you specified.

[ - ]
Reply by SpiderKennyApril 21, 2016

160 bits at 800 MHz - If my maths is correct, then that is about 800 x 1,000,000 x 160 which is 128 GBytes per second. Is that correct?

This must be some pretty high-end stuff, so I suspect cost is not an issue.

Therefore get the best PCB design and analysis tools and run timing, slew, crosstalk calculations and so on.

(Presumably some of those 160 bits are error correction bits?, still it doesn't affect the delivery rate!)