FPGARelated.com
Forums

HDL to Schematic Reporting

Started by Sanram 6 years ago5 replieslatest reply 6 years ago894 views

I am looking at a tool (or combination of tools) to perform the following. Please advise.

1) Read Verilog/VHDL RTL input code and convert it to technology independent block & gate level representation

2) Able to export the gate level diagram from the tool into a visio / pdf / word - editable diagrams.

I am aware of tools like HDL Analyzer which comes from Synopsys / other synthesis tools but not sure they can do #2 above.

[ - ]
Reply by martinthompsonMay 19, 2018

1) is achievable by most (all?) synthesis tools.  Admittedly the FPGA vendor ones will not be technology independent :)

2) is trickier... 

I think Renoir (Mentor?) used to be able to produce nice diagrams which were also editable, but only in that tool.

I've had a quick Google and found EASE:https://www.hdlworks.com/products/ease/documentati... which can export to SVG, which should then be editable in a vector tool (like Inkscape).

Sigasi (http://insights.sigasi.com/manual/views.html) can also export block diagrams and state machines as SVG.  But not a gate-level post-synth type view...

Looking forward to other answers :)

[ - ]
Reply by SanramMay 19, 2018

Thanks for your inputs.

On #1 in your post, its true that post synthesis and P&R it is no longer tech. independent. However several tools (e.g. Synplify Pro) provide a tech independent hierarchical or flattened view of RTL in gate level representation (using distinctive logic gate symbol). But they are not editable. 

My requirement is to have a 1-to-1 RTL-to-gate level representation with hierarchical and flattened view.

I will try Renoir option mentioned by you - hope that helps. But as you say if it is only editable in the tool and not exportable to a report / document, that may not help

Incidentally I did stumble upon the EASE tool you have mentioned and am trying that as well. But from the experiments done, it is not giving a real logic gate representation of the underlying RTL code. Rather it provides its own convenient block level view of the logic tracing to the RTL code. But it does have the option of exporting the diagrams to PDF or SVG. Further investigating...

I haven't used Inkscape - but seems to be good tool for SVG.

Sigasi seems to be a nice tool but it says it supports only VHDL and SystemVerilog. Some features seems support only VHDL per their documentation. Need to see if Verilog also is supported. I will try this tool as well.

Thanks again.



[ - ]
Reply by david_daysMay 19, 2018

I use Inkscape all the time--it's a good free tool for creating/editing SVG files.  (As examples, most of the images on my articles are made or finished with Inkscape.)


If you can get something to output an SVG file (or several), you might be able to use Inkscape to manipulate and combine them as necessary.

[ - ]
Reply by martinthompsonMay 19, 2018

Agree - I've not seen anything else quite like Synplify's view (in terms of gate-level views) - but even that is not gates, but technology specific.

I think all the other tools are primarily for visualising block diagrams, as you note.

Out of interest, why do you want to do this?  It seems most other people don't (or have found other ways around the problem) - otherwise there would be a load of tools :)


[ - ]
Reply by SanramMay 19, 2018

Well, as a consultant, I have been tasked with improving a design flow process followed by a vendor and in that process improving team's performance and productivity. Please bear with the long post below.

At present, the design flow (this has been going on for an year or so) involves more or less in the following sequence, by the vendor:

1) Receive legacy Verilog RTL (usually sub blocks of an overall system) from customer along with other minimal set of information.

2) Analyze the design represented by the RTL code for its functionality and timing - this the vendor team surprisingly has been doing manually by wading through the code, paper and pen, diagrams on visio etc.

3) As an outcome of step 2, create functional specifications document (used for verification also) followed by implementation specification document (MSWord containing Visio diagrams).

4) For the implementation spec, a detailed gate level representation (tech. independent) to be included. Apparently this is the process being aligned and agreed with customer for past 1-1.5 years

5) The customer uses these documents for design representation and for future modifications as needed.

Now I enter here to help a) improve process flow / productivity of the vendor team b) subsequently help vendor convince the customer to incorporate the new flow.

So I am looking at appropriate tool(s) to a) extract the legacy code to a gate level representation (easy thing to do) b) edit and/or report / store that diagram into an acceptable format for future updates as needed. Note that the diagram may contain some annotation added for better understanding. Hence the need for editing the diagram.

That's the story!