VHDL tutorial - Creating a hierarchical design
Complex VHDL files quickly become hard to read and maintain. This tutorial demonstrates how to break a design into reusable entities by building a divide-by-10 component, explaining ports, sensitivity lists, and the inout usage for a toggled output. It then shows how to instantiate and chain three instances into a ÷1000 divider, with synthesis notes from compiling to an XC2C128 device.
VHDL tutorial - combining clocked and sequential logic
Need the ADC clock to sometimes be the raw 40MHz input? Gene Breniman shows how to extend a reloadable, counter-based VHDL clock divider to support a master-clock pass-through by using a conditional signal assignment to switch between the internal ADCClk and Mclk. The article also covers remapping ClkSel values and includes a working XC2C32A CPLD build that leaves room for future enhancements.
Designing Embedded Systems with FPGA-2
Turning an FPGA hardware design into a running embedded system is mostly tool work. This post walks through using Xilinx EDK to compile a base design into a .bit bitstream, generate libraries and board support packages from .mhs and .mss files, and build MicroBlaze applications with GCC. It highlights the default boot placement at 0x0 and why some apps need an explicit execution transfer.
VHDL tutorial - part 2 - Testbench
In this follow-up Gene Breniman builds a VHDL testbench in Xilinx ISE, showing how to generate a continuous master clock, apply a power-on reset, and sequence register strobes to change clock divisors. He walks through timing waits and observation delays needed to verify ADC clock rates. The article also shows how simulation exposed a copy-paste bug in the original design.
Designing Embedded System with FPGA - 1
Getting an embedded system running on an FPGA is much simpler than it sounds when you use Xilinx EDK and a soft processor. Pragnesh Patel walks through a beginner-friendly approach using the MicroBlaze CPU, drag-and-drop IP cores, and a Spartan-3E starter kit so you can assemble peripherals without deep VHDL knowledge. The post focuses on the EDK base system builder and first setup steps to generate a working design.
VHDL tutorial
Gene Breniman presents a hands-on VHDL walkthrough for a programmable clock divider implemented on a Xilinx CoolRunner CPLD (XC2C32A). The example shows how to declare ports and internal signals, implement a clock-division process with reset and falling-edge detection, and create a simple addressable latch to select clock rates from a 40MHz master clock. It’s a compact, practical guide for embedded engineers learning VHDL and CPLD design.
New Discussion Group: DSP & FPGA
I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to: fpgadsp-subscribe@yahoogroups.com
As usual, it should take a few weeks before there are enough members for interesting discussions to get started.
MyHDL Presentation Examples
Christopher Felton collected slide-ready MyHDL demos he used at EELive and PyOhio, making it easy to see practical HDL examples in action. The post explains the tradeoffs behind single-slide examples, links to 2013 and 2014 demos from simple FPGA hello-worlds to filters and a VGA system, and points readers to the repository where full and larger examples live for reuse.
Cutting a Path Forward
As a software developer building a drone navigation prototype, the author turned to FPGAs after realizing CPUs and cloud tethering break the "simple, cheap, reliable" constraints. He proposes mapping sensor probabilities into a graph-cut network using negative log-likelihoods to produce risk‑averse, real‑time path planning, aiming for tens of milliseconds. The post explains the graph-cut idea, cites FPGA precedents, and lays out a practical FPGA-focused plan of attack.
Holy Bit Bucket
Christopher Felton reacts to Tabula's 'Spacetime' pitch, which claims an 8x boost in LUT density by time-division multiplexing internal logic. He urges caution, comparing Tabula to Achronix and pointing out that early parts will likely target high-end networking and carry premium pricing. The post argues inexpensive development boards will be crucial for wider adoption.
What do Ohio, Python, and FPGAs have in common?
Christopher Felton is bringing MyHDL, Python, and hands-on FPGA work to the free pyohio regional conference on July 27-28. His informal talk introduces programmable hardware to imperative thinkers, contrasts FPGAs with modern computers, and showcases the MyHDL package. The follow-up workshop lets Python programmers edit an example, configure a Xess development board, and see their changes run on real hardware.
New Design - Finally!
Stephane has finally applied a modern design to FPGARelated.com, bringing the site in line with DSPRelated.com and EmbeddedRelated.com. After a long todo list the refreshed layout and updated styling are live, promising a cleaner, more consistent experience across his engineering sites. Drop by to explore the new look and share feedback with the author.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
MyHDL Presentation Examples
Christopher Felton collected slide-ready MyHDL demos he used at EELive and PyOhio, making it easy to see practical HDL examples in action. The post explains the tradeoffs behind single-slide examples, links to 2013 and 2014 demos from simple FPGA hello-worlds to filters and a VGA system, and points readers to the repository where full and larger examples live for reuse.
Summer of Gateware
Christopher Felton walks through MyHDL's first year as a Google Summer of Code sub organization, from selecting two students to shipping SDRAM and conversion work. He highlights the practical bumps, including proposal expectations, the value of early patches, and the need for frequent mentoring and flexible milestones. The post shares concrete lessons for mentors, students, and projects planning to participate in GSoC.
New Design - Finally!
Stephane has finally applied a modern design to FPGARelated.com, bringing the site in line with DSPRelated.com and EmbeddedRelated.com. After a long todo list the refreshed layout and updated styling are live, promising a cleaner, more consistent experience across his engineering sites. Drop by to explore the new look and share feedback with the author.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
MyHDL @EDAPlayground
MyHDL just got easier to try: it's available on EDAPlayground, so you can run Python-based HDL verification directly in the browser. The two-panel editor places the testbench on the left and the HDL under test on the right, with public examples such as a simple strobe and a RAM test ready to copy. Christopher Felton also links a curated resource list to help you get started quickly.
A Bit Bucket had Holes
Christopher Felton looks back at TierLogic's multi-layer FPGA idea and its recent shutdown, contrasting it with Tabula's virtual 3D approach. He asks whether physical-layer stacking could have delivered the ultra-high logic density some designs need, especially at modest clock rates and small footprints. The post highlights how funding, market fit, and patent outcomes often decide whether neat FPGA tech becomes a product.
Holy Bit Bucket
Christopher Felton reacts to Tabula's 'Spacetime' pitch, which claims an 8x boost in LUT density by time-division multiplexing internal logic. He urges caution, comparing Tabula to Achronix and pointing out that early parts will likely target high-end networking and carry premium pricing. The post argues inexpensive development boards will be crucial for wider adoption.
