VHDL tutorial - A practical example - part 1 - Hardware
Gene Breniman walks through a practical CPLD-based data acquisition engine built for a low-power handheld instrument, focusing on hardware choices, signal flow, and pin assignments. The article explains component selection including a PCM1870 ADC, CY14B101Q2 serial nvSRAM, and an XC2C64A CPLD, and shows how the CPLD acts as an SPI sequencer and I2S clock master while minimizing microcontroller pins and power draw.
Introduction to FPGA Technology
Muhammad Yasir lays out a concise primer on FPGA fundamentals, covering internal architecture, vendors, and practical selection criteria. He explains how logic cells, LUTs, flip-flops, carry chains, block RAM, and I/O blocks combine to determine capacity and performance. This friendly overview shows why FPGAs beat ASICs for low-volume or rapidly changing designs, and how to match device resources to your application needs.
FPGA Bloggers Needed - New Reward System
You can earn up to $500 for a single FPGA blog post on FPGARelated. Stephane Boucher announces a new pageview-based reward system that pays $25 for every 250 unique pageviews, capped at $500 when a post reaches 5,000 views. If you write about Verilog, VHDL, or FPGA design and want to share expertise while getting paid, fill the short application form to apply.
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
A Bit Bucket had Holes
Christopher Felton looks back at TierLogic's multi-layer FPGA idea and its recent shutdown, contrasting it with Tabula's virtual 3D approach. He asks whether physical-layer stacking could have delivered the ultra-high logic density some designs need, especially at modest clock rates and small footprints. The post highlights how funding, market fit, and patent outcomes often decide whether neat FPGA tech becomes a product.
Developing FPGA-DSP IP with Python
Designing FPGA-DSP IP entirely in Python is practical and productive, as Christopher Felton demonstrates using MyHDL. He shows how numpy and scipy handle the signal design while a SIIR class generates RTL, enables side-by-side floating-point and HDL simulation, and converts to Verilog for synthesis. The post includes Xilinx XC3S500E resource results and a link to the SIIR source on BitBucket, making it easy to try the workflow.
Holy Bit Bucket
Christopher Felton reacts to Tabula's 'Spacetime' pitch, which claims an 8x boost in LUT density by time-division multiplexing internal logic. He urges caution, comparing Tabula to Achronix and pointing out that early parts will likely target high-end networking and carry premium pricing. The post argues inexpensive development boards will be crucial for wider adoption.
The Spartans
Christopher Felton walks through the Spartan6 FPGA basics, explaining CLBs, slices, and the new 6-input LUTs while comparing them to Spartan3. He ran timing-driven mappings of real gateware to show practical LUT utilization differences. The post gives a pragmatic estimate of expected LUT savings and points out where mapping results can vary depending on the design.
New Design - Finally!
Stephane has finally applied a modern design to FPGARelated.com, bringing the site in line with DSPRelated.com and EmbeddedRelated.com. After a long todo list the refreshed layout and updated styling are live, promising a cleaner, more consistent experience across his engineering sites. Drop by to explore the new look and share feedback with the author.
Point of View
Christopher defends a straightforward MyHDL RTL description of a FIR filter, arguing it is explicit, readable, and concise. He compares that style to a functional hardware description built with Python primitives and list comprehensions, and finds both convert to identical synthesis resources for this example. The post highlights readability tradeoffs and suggests choice often comes down to background and preference.
Summer of Gateware
Christopher Felton walks through MyHDL's first year as a Google Summer of Code sub organization, from selecting two students to shipping SDRAM and conversion work. He highlights the practical bumps, including proposal expectations, the value of early patches, and the need for frequent mentoring and flexible milestones. The post shares concrete lessons for mentors, students, and projects planning to participate in GSoC.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
Are you kidding me?
Christopher Felton pushes back on the idea that C/C++/SystemC are the natural path to higher-abstraction FPGA design. He argues hardware designers often do not use C-family languages for modeling and simulation, so choosing C as the HLS lingua franca may be more about tool momentum than suitability. The post urges reconsidering languages with higher abstraction and lower cost of entry for system modeling and HLS.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
[Comments] C HLS Benefits
Christopher Felton argues C-to-gate HLS showed little advantage in his median calculation comparison with MyHDL. He explains the test mixes language paradigm and abstraction: Vivado C HLS is an imperative, step-by-step style while MyHDL offers a concurrent, HDL-level description with Python's readability and elaboration features. He notes C-HLS can help if you only know C, but for massively parallel FPGA work non-C tools may be preferable.
Cutting a Path Forward
As a software developer building a drone navigation prototype, the author turned to FPGAs after realizing CPUs and cloud tethering break the "simple, cheap, reliable" constraints. He proposes mapping sensor probabilities into a graph-cut network using negative log-likelihoods to produce risk‑averse, real‑time path planning, aiming for tens of milliseconds. The post explains the graph-cut idea, cites FPGA precedents, and lays out a practical FPGA-focused plan of attack.
Holy Bit Bucket
Christopher Felton reacts to Tabula's 'Spacetime' pitch, which claims an 8x boost in LUT density by time-division multiplexing internal logic. He urges caution, comparing Tabula to Achronix and pointing out that early parts will likely target high-end networking and carry premium pricing. The post argues inexpensive development boards will be crucial for wider adoption.
FPGA Bloggers Needed - New Reward System
You can earn up to $500 for a single FPGA blog post on FPGARelated. Stephane Boucher announces a new pageview-based reward system that pays $25 for every 250 unique pageviews, capped at $500 when a post reaches 5,000 views. If you write about Verilog, VHDL, or FPGA design and want to share expertise while getting paid, fill the short application form to apply.
Homebrew CPUs: Color Languages
Victor Yurkovsky proposes turning color from mere syntax highlighting into a semantic tool for a Forth-like CPU, letting color pick which stack an operation touches. He outlines a "Rainbow Forth" where green and blue select two datastacks, red denotes the return stack, gray means use the caller's color, and white is neutral. The post sketches CPU changes, a COLOR register, call encoding and immediate-mode coloring, and teases editor and compiler implications for implementing this idea on a J1-style core.
Tool install for examples
The post explains the toolchain and installs needed to compile the FPGARelated MyHDL examples. It notes that examples use MyHDL for hardware description and the myhdl_tools/rhea.build Python packages to drive the FPGA vendor tools, so the full flow runs from a Python environment. The author lists required installs: MyHDL (pip or GitHub), myhdl_tools (Bitbucket), the rhea.build automation package, and the FPGA vendor toolchains (Xilinx ISE WebPACK, Altera Quartus, Lattice Diamond). Board-specific programming utilities such as fpgalink and xstools are also required for various development boards. Most examples live in a Bitbucket repository or gist and include a test_and_build_.py script that automates convert, synthesize, map, place-and-route, and bitfile generation. A 2015 changelog notes some tools were deprecated and repository locations were updated.
Cutting a Path Forward
As a software developer building a drone navigation prototype, the author turned to FPGAs after realizing CPUs and cloud tethering break the "simple, cheap, reliable" constraints. He proposes mapping sensor probabilities into a graph-cut network using negative log-likelihoods to produce risk‑averse, real‑time path planning, aiming for tens of milliseconds. The post explains the graph-cut idea, cites FPGA precedents, and lays out a practical FPGA-focused plan of attack.
Are you kidding me?
Christopher Felton pushes back on the idea that C/C++/SystemC are the natural path to higher-abstraction FPGA design. He argues hardware designers often do not use C-family languages for modeling and simulation, so choosing C as the HLS lingua franca may be more about tool momentum than suitability. The post urges reconsidering languages with higher abstraction and lower cost of entry for system modeling and HLS.
Choosing an Implementation Approach
I outline why I chose a CPU-like Graph Cut Processing Unit for FPGA-based graph-cut work, contrasting whole-problem and streaming approaches from the literature. The plan maps push-relabel style augmenting-path iterations to a simple GCPU state machine and pseudocode, prioritizing staged, testable development now and leaving highly parallel streaming scaling for later.
Summer of gateware is coming (again)
Wondering what gateware will come out of this summer? Christopher Felton announces MyHDL is back in Google Summer of Code and has been awarded six student slots. Projects span GEMAC, a Leros tiny processor, JPEG encoder front/backends, RISC-V tooling and HDMI+RISC-V work. Follow along for short project updates and a final summer summary.
[Comments] C HLS Benefits
Christopher Felton argues C-to-gate HLS showed little advantage in his median calculation comparison with MyHDL. He explains the test mixes language paradigm and abstraction: Vivado C HLS is an imperative, step-by-step style while MyHDL offers a concurrent, HDL-level description with Python's readability and elaboration features. He notes C-HLS can help if you only know C, but for massively parallel FPGA work non-C tools may be preferable.
Point of View
Christopher defends a straightforward MyHDL RTL description of a FIR filter, arguing it is explicit, readable, and concise. He compares that style to a functional hardware description built with Python primitives and list comprehensions, and finds both convert to identical synthesis resources for this example. The post highlights readability tradeoffs and suggests choice often comes down to background and preference.
What do Ohio, Python, and FPGAs have in common?
Christopher Felton is bringing MyHDL, Python, and hands-on FPGA work to the free pyohio regional conference on July 27-28. His informal talk introduces programmable hardware to imperative thinkers, contrasts FPGAs with modern computers, and showcases the MyHDL package. The follow-up workshop lets Python programmers edit an example, configure a Xess development board, and see their changes run on real hardware.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
