Libero SmartFusion 2 Pinout Chart

Started by cwible 5 months ago25 views
Hi everyone, I am trying to learn how to use the SmartFusion 2 Maker Kit for a research project. Right now I am trying to simply flash an LED but I cant find which...

Clock domain crossing

Started by vpsampath 6 months ago50 views
Constraints are essential when developing a new design. The constraints set up are the environmental, clock, test and power boundaries the designers must keep themselves...

Creating custom IP for zedboard

Started by shlomishab 6 months ago34 views
Hi all,I'm working on a video streming project with a zedboard and an ov7670 camera module. I found a similar project online, made by Mike Field, and I was able...

TinyFPGA BX Creating Two OR Gates

Started by Joe3502 9 months ago1 replylatest reply 6 months ago35 views
Hi all,  First off, I hope that you and your families are staying safe and well during this time of global pandemic.  I just received my TinyFPGA in the mail yesterday...
Hello everyone,I am migrating an old MAXPLUS II design to Quartus II. I could transfer the schematic files and the design is ready, but not able to migrate the...

Processing Gain at output of ADC

Started by rathnakarreddy 8 months ago2 replieslatest reply 8 months ago56 views
With adequate filtering after AD conversion, the SNR is calculated as,SNR=6.02*N+1.76+10*log(fs/(2*BW));N-> No: of ADC bitsThe term 10log(fs/2*BW) is referred...

How to avoid Blocking Statement in Verilog

Started by rathnakarreddy 8 months ago1 replylatest reply 8 months ago51 views
Hi,I have a matlab code and I have to convert it to verilog.The matlab code is as follows:/****************************************************************/clc;clear...

ADC SNR and Processing Gain

Started by rathnakarreddy 8 months ago3 replieslatest reply 8 months ago45 views
Hi,with reference to the following article, have understood that decimating doesn't destroy the processing...

How to make sure clock is from the main clock tree?

Started by andy92806 9 months ago6 replieslatest reply 8 months ago32 views
Let's say you have a module that needs a clock like this:module need_clk(i_clk, .....) input i_clk;. .......endmoduleAt the top level, you then have a statement...

Block Floating Point in FFT.

Started by matiasgg 8 months ago15 replieslatest reply 8 months ago156 views
Hi. I've seen other post like this on the forum, but it is still not clear to me so I will ask. Sorry if it seems like a repost.I'm creating an FFT/IFFT in verilog...

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