Forums

Aldec Active-HDL vs Modelsim PE state of play.

Started by glenenglish 1 year ago2 replieslatest reply 1 year ago80 views
What's the state of play here  in 2021 ? I have had a Modelsim PE seat in maintenance for 16 years. Modelsim has not changed, improved any done anything in that...

Sha256 on FPGA board

Started by Iani97 1 year ago102 views
Hello guys,I have been trying to implement to implement the SHA256 algorithm on my ARTY A7 35t using VivadoI am using TeraTerm to send information to the board...

RC-filter in VHDL

Started by Aida92 1 year ago1 replylatest reply 1 year ago94 views
Hello everyone!I am trying to implement Raised-cosine filter in VHDL. In the current simulation I am using the standard method of the filter simulation:- create...

Doubt about constraining external input

Started by simonzz 1 year ago4 replieslatest reply 1 year ago67 views
Hi all,I am usig an AD9914 DDShttps://www.analog.com/media/en/technical-documentation/data-sheets/AD9914.pdfwith its DROVER output connected to a I/O of the FPGA...

Implementing a folded FIR on FPGA

Started by DHMarinov 1 year ago2 replieslatest reply 1 year ago75 views
Hello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...

Efficient implementation of FIR filters on a FPGA

Started by DHMarinov 1 year ago2 replieslatest reply 1 year ago99 views
Hello there,I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here: PS:I'd...

Xilinx FIR Compiler Fractional Rate Converter

Started by ismailt42 1 year ago1 replylatest reply 1 year ago69 views
Hello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...

Polyphase Filter Bank channelizer issue

Started by epetragl 2 years ago5 replieslatest reply 2 years ago532 views
Hello, I am currently studying the implementation of a Polyphase Filter Bank channelizer designed by Xilinx in its XAPP1161. The architecture is composed by a single...

UART communication For Nexys A7-100t

Started by MCU231 2 years ago1 replylatest reply 2 years ago300 views
Hello,I'm new to UART for FPGA and recently I tried a demo project that I found at: https://www.fpga4fun.com/SerialInterface.htmlMy problem is using RxD_data_ready...

Zedboard and the ov7670 settings

Started by shlomishab 2 years ago120 views
I've been working on a video streaming project using a zedboard and the ov7670 camera. My project is based on this one (capture and vga .vhd files): https://www.hackster.io/dhq/fpga-camera-system-14d6ea...

Registering will allow you to participate to the forums on ALL the related sites and give you access to all pdf downloads.

Sign up

I agree with the terms of use and privacy policy.

Try our occasional but popular newsletter. VERY easy to unsubscribe.
or Sign in