Forums
HiI have a zedboard and a nexys video artix 7 board. I am generating a sinusoid from DDS Core of the same frequency (by supplying the same phase increment and the...

Tips for using Xilinx Ultra RAMs

Started by weetabixharry 4 months ago2 replieslatest reply 4 months ago49 views
What are the main considerations that I should be aware of if I want to use Ultra RAMs in my design?I am familiar with the Block RAMs used in 5-, 6- and 7-series...

recovery/removal violations, does it always matter?

Started by kaz 4 months ago9 replieslatest reply 4 months ago36 views
Hi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...

FPGA output pulsating in real time

Started by abdul_samad 4 months ago1 replylatest reply 4 months ago27 views
Hi,I am working on a digital down conversion module for a project of mine. The module down converts a  signal at IF 455 KHz received through an ADC, multiplies...

Fixed Point Library for Python

Started by smlgit 4 months ago7 replieslatest reply 4 months ago208 views
Hi everyone,As part of a large FPGA/DSP project, I built a c extension library for python that mimicks the vhdl standard library fixed point functionality (https://github.com/smlgit/fpbinary)....

register clear on read

Started by kamalovich 5 months ago4 replieslatest reply 4 months ago68 views
hi all !I am doing a BER (BIT ERROR RATE) in vhdl and I have to put 2 registers clear on read which counts the number of words in error and the number of bits...

Spammers are getting more sophisticated

Started by stephaneb 5 months ago4 replieslatest reply 5 months ago249 views
Just a quick post to inform you of a scheme used by spammers lately on the Related sites.Here's the scheme:They create an account on one of the Related sites and...

metastabilty with multicycle

Started by nori 5 months ago3 replieslatest reply 5 months ago42 views
Hi All,This thought occurred to me regarding multicycle path.Assume I set multicycle of 2. Then this implies that data delay from launch edge(0) will respect the...

fpga spartan 6 io ports are no longer working

Started by ahmed1600 6 months ago2 replieslatest reply 6 months ago30 views
HELLO there,i have spartan 6 of the familyxlc9  but i am facing a severe problem with it . first i can burn successfully with jtag on it .its power is okay but...

Live Streaming #3

Started by stephaneb 6 months ago9 replieslatest reply 6 months ago94 views
Today's live streaming will be short - one quick draw and then testing of the split screen.

Registering will allow you to participate to the forums on ALL the related sites and give you access to all pdf downloads.

Sign up

I agree with the terms of use and privacy policy.

Try our occasional but popular newsletter. VERY easy to unsubscribe.
or Sign in