Using a single DSP48E2 Slice to infer three 48-bit inputs adder

Started by learni 5 years ago1 replylatest reply 1 year ago328 views
Hi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(https://www.xilinx.com/support/answers/66429.html).I...

LVDS as a comparator

Started by Tanu3 4 years ago1 replylatest reply 1 year ago192 views
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal...

Lattice FPGA timing constraint help

Started by dave94024 4 years ago5 replieslatest reply 1 year ago558 views
I have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior.  I'm pretty sure it's due to timing constraint issues...

Aldec Active-HDL vs Modelsim PE state of play.

Started by glenenglish 3 years ago3 replieslatest reply 1 year ago362 views
What's the state of play here  in 2021 ? I have had a Modelsim PE seat in maintenance for 16 years. Modelsim has not changed, improved any done anything in that...

RC-filter in VHDL

Started by Aida92 3 years ago2 replieslatest reply 1 year ago183 views
Hello everyone!I am trying to implement Raised-cosine filter in VHDL. In the current simulation I am using the standard method of the filter simulation:- create...

FPGA speed and timing closure metrics

Started by kaz 3 years ago3 replieslatest reply 1 year ago109 views
We have plenty data sheets, documents, forum replies and videos on various fpgas and designs. However what is missing in all cases is some idea how fast can one...

FPGA for audio DSP

Started by RogerG 2 years ago7 replieslatest reply 1 year ago1735 views
I am a complete beginner when it comes to FPGA so any advice would be helpful.I have been looking at updating my audio system which currently takes an analogue...

FPGA - how to receive and use external trigger

Started by wwz 2 years ago1 replylatest reply 1 year ago80 views
Appreciate any specific help or general guidance to my question below:Suppose I have two FPGAs: FPGA_master and FPGA_slave.On FPGA_master I can generate an internal...

Learning FPGA

Started by stephaneb 6 years ago19 replieslatest reply 1 year ago4459 views
A few months ago, this community tackled the first FPGA FAQ titled When (and why) is it a good idea to use an FPGA in your embedded system design?.  Your contributions...

When (and why) is it a good idea to use an FPGA in your embedded system design?

Started by stephaneb 6 years ago12 replieslatest reply 1 year ago7937 views
Once we are done with this thread, the vision is for readers to get a basic understanding of when should an FPGA be considered in the design of an Embedded System...

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