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Activating CH7301 on SP605 board #xilinx #vhdl
Started by 4 months ago●2 replies●latest reply 4 months ago●53 viewsHelloI am working on a project using the SP605 for a video
application. Currently I'm trying to output a picture via the DVI output
which is driven by a CH7301...
remains a black box sine it has not binding entity
Started by 5 months ago●7 replies●latest reply 5 months ago●119 viewsHI
I'm working on a design where I have implemented an I2C module which I'm trying to use as a component in another piece of VHDL.
The problem I've got is that...
Hi all,Referring to this doc on A law compression (table 1):http://www.young-engineering.com/docs/YoungEnginee...The table is meant for 13 bits signed to 8 bits...
Lattice: Utilization and Clock Report
Started by 6 months ago●3 replies●latest reply 5 months ago●27 viewsHello,I have only one clock in my design and the number of clock load in my clock report(.par) does not correspond to the number of the registers in the map report(.mrp),...
simple line drive generator doesn't work properly
Started by 5 months ago●3 replies●latest reply 5 months ago●28 viewsHi guysI don't have any real-world experience with synthesizable VHDL and FPGA's but I've been really curious about it for a long time. So I've found an old experimenter's...
Synchronizing clock cycles of FPGA in Mojo V3 with the clock cycle of a signal generator
Started by 6 months ago●4 replies●latest reply 6 months ago●84 viewsHi, So I want to synchronize the clock cycle of an FPGA in mojo V3 development board, whose default clock cycle is 50 MHz with a function generator. Currently,...
Hello! I am currently working on a matrix multiplication project. After performing the multiplication of the matrices, I am trying to build a module that can write...
VHDL Matrix Multiplication using UART and BRAM
Started by 7 months ago●2 replies●latest reply 7 months ago●112 viewsMy project involves performing matrix multiplication in vhdl. The two input matrices (8 bits each) are sent using a terminal and received via UART Rx. The FPGA...
Implementing octave algorithm in FPGA using c++
Started by 7 months ago●11 replies●latest reply 7 months ago●254 viewsI am currently working on writing a scrambler and DeScrambler code for Orthogonal Frequency Division Multiplexing(OFDM). I am planning to write an algorithm for...
Searching for info about very old FPGA devices
Started by 8 months ago●3 replies●latest reply 8 months ago●63 viewsHello. My name is Rodrigo and I am from Argentina. I was looking for very old datasheets without success :-( (I searched a lot in google, archive.org, alldatasheets,...
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