Hello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...

Hello, I am currently studying the implementation of a Polyphase Filter Bank channelizer designed by Xilinx in its XAPP1161. The architecture is composed by a single...

Hello,I'm new to UART for FPGA and recently I tried a demo project that I found at: https://www.fpga4fun.com/SerialInterface.htmlMy problem is using RxD_data_ready...

I've been working on a video streaming project using a zedboard and the ov7670 camera. My project is based on this one (capture and vga .vhd files): https://www.hackster.io/dhq/fpga-camera-system-14d6ea...

I have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to implement the...

Hello,I am a newbie in verifying complex FPGA designs.  In my testbench, I am reading the test vectors from  a text file and assigning them to the input ports...

Hey guys! My masters degree thesis is digital lock-in amplifier. I want to make it on an FPGA to learn this piece of hardware. Basically I have a budget of 220€...

Hello,I have the following questions:1. A Quartus Prime Lite version is sufficient for my FPGA design. Can I use only the Lite version in my company for commercial...

Hi everyone, I am trying to learn how to use the SmartFusion 2 Maker Kit for a research project. Right now I am trying to simply flash an LED but I cant find which...

Constraints are essential when developing a new design. The constraints set up are the environmental, clock, test and power boundaries the designers must keep themselves...