Deep-learning FPGA. How did you?

Started by SpiderKenny 8 months ago6 replieslatest reply 8 months ago91 views
Maybe I'm one of the worst people to be learning FPGAs because I've been a firmware developer on embedded CPUs and an application developer on Mac / Windows for...

cout in FPGA

Started by WCH 9 months ago1 replylatest reply 8 months ago61 views
Hello, I am new to FPGA. I have seen a template in DE0-nano. I would like to display the value in "PWM_width <= PWM_width[5:0]+ PWM_adj;" one by one in a screen...

FPGA Clocking

Started by HGola 9 months ago3 replieslatest reply 9 months ago75 views
I have Nexys4 FPGA , it has a system clock of 100mhz, can it generate 200mhz clock, when using Clocking Wizard IP?

DueProLogic by EarthPeopleTechnology: Help making it work?

Started by AwesomeCronk 3 years ago5 replieslatest reply 10 months ago148 views
I was given a DueProLogic(DPL) board last year as a birthday gift. I never could get it to work. After having built my desktop and having installed Quartus and the...

Vivado Tcl

Started by Kocsonya 1 year ago3 replieslatest reply 1 year ago135 views
I'd like to use Vivado in non-project mode, using makefiles and Tcl scripts. However, my chip is a Zynq-7000 SoC where Vivado needs to generate a module representing...

set multicycle path contradiction on hold value

Started by kaz 1 year ago205 views
Trying to solve the following contradiction about "set_multicycle_path"case 1: "Vivado using constraints" pdf states that for most cases of timing relaxing multicycle...

FPGA speed and timing closure metrics

Started by kaz 2 years ago2 replieslatest reply 2 years ago76 views
We have plenty data sheets, documents, forum replies and videos on various fpgas and designs. However what is missing in all cases is some idea how fast can one...

Aldec Active-HDL vs Modelsim PE state of play.

Started by glenenglish 2 years ago2 replieslatest reply 2 years ago91 views
What's the state of play here  in 2021 ? I have had a Modelsim PE seat in maintenance for 16 years. Modelsim has not changed, improved any done anything in that...

Sha256 on FPGA board

Started by Iani97 2 years ago105 views
Hello guys,I have been trying to implement to implement the SHA256 algorithm on my ARTY A7 35t using VivadoI am using TeraTerm to send information to the board...

RC-filter in VHDL

Started by Aida92 2 years ago1 replylatest reply 2 years ago107 views
Hello everyone!I am trying to implement Raised-cosine filter in VHDL. In the current simulation I am using the standard method of the filter simulation:- create...

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