Activating CH7301 on SP605 board #xilinx #vhdl

Started by ajellis 4 months ago2 replieslatest reply 4 months ago53 views
HelloI am working on a project using the SP605 for a video application. Currently I'm trying to output a picture via the DVI output which is driven by a CH7301...

remains a black box sine it has not binding entity

Started by ajellis 5 months ago7 replieslatest reply 5 months ago119 views
HI I'm working on a design where I have implemented an I2C module which I'm trying to use as a component in another piece of VHDL. The problem I've got is that...

A Law compression for FPGA

Started by kaz 5 months ago7 replieslatest reply 5 months ago55 views
Hi all,Referring to this doc on A law compression (table 1): table is meant for 13 bits signed to 8 bits...

Lattice: Utilization and Clock Report

Started by cubosubtil 6 months ago3 replieslatest reply 5 months ago27 views
Hello,I have only one clock in my design and the number of clock load in my clock report(.par) does not correspond to the number of the registers in the map report(.mrp),...

simple line drive generator doesn't work properly

Started by ombz 5 months ago3 replieslatest reply 5 months ago28 views
Hi guysI don't have any real-world experience with synthesizable VHDL and FPGA's but I've been really curious about it for a long time. So I've found an old experimenter's...

Synchronizing clock cycles of FPGA in Mojo V3 with the clock cycle of a signal generator

Started by embeddedelectronics 6 months ago4 replieslatest reply 6 months ago84 views
Hi, So I want to synchronize the clock cycle of an FPGA in mojo V3 development board, whose default clock cycle is 50 MHz with a function generator. Currently,...


Started by maha_66 6 months ago3 replieslatest reply 6 months ago90 views
Hello! I am currently working on a matrix multiplication project. After performing the multiplication of the matrices, I am trying to build a module that can write...

VHDL Matrix Multiplication using UART and BRAM

Started by maha_66 7 months ago2 replieslatest reply 7 months ago112 views
My project involves performing matrix multiplication in vhdl. The two input matrices (8 bits each) are sent using a terminal and received via UART Rx. The FPGA...

Implementing octave algorithm in FPGA using c++

Started by Abhinav90 7 months ago11 replieslatest reply 7 months ago254 views
I am currently working on writing a scrambler and DeScrambler code for Orthogonal Frequency Division Multiplexing(OFDM). I am planning to write an algorithm for...

Searching for info about very old FPGA devices

Started by rodrigomelo9 8 months ago3 replieslatest reply 8 months ago63 views
Hello. My name is Rodrigo and I am from Argentina. I was looking for very old datasheets without success :-( (I searched a lot in google,, alldatasheets,...

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