Forums
How to avoid Blocking Statement in Verilog
Started by 6 years ago●1 reply●latest reply 6 years ago●113 viewsHi,I have a matlab code and I have to convert it to verilog.The matlab code is as follows:/****************************************************************/clc;clear...
Hi,with reference to the following article,https://www.dsprelated.com/showthread/comp.dsp/727...I have understood that decimating doesn't destroy the processing...
How to make sure clock is from the main clock tree?
Started by 6 years ago●6 replies●latest reply 6 years ago●317 viewsLet's say you have a module that needs a clock like this:module need_clk(i_clk, .....) input i_clk;. .......endmoduleAt the top level, you then have a statement...
Hi. I've seen other post like this on the forum, but it is still not clear to me so I will ask. Sorry if it seems like a repost.I'm creating an FFT/IFFT in verilog...
Does anyone have experience in RFSoCs?
Started by 6 years ago●10 replies●latest reply 6 years ago●721 viewsHello everyone!Our lab has bought the Xilinx ZCU1275 RFSoC and we, being Masters students are finding it extremely difficult to learn how to control the board. Since...
Hi,
I'm taking an electronics class for college and I am very behind because
of some family issues that I've been dealing with. I need to pass this
class to graduate.
I...
Hello everybody,I am searching for a WYSIWYG software to draw, from complex to simple, block diagrams for documenting my personal projects. So far I am using CircuiTikz...
OT: Laughing in the Face of Adversity
Started by 6 years ago●14 replies●latest reply 6 years ago●677 viewsHumor helps us take back control and to connect - two things we have lost in our fight against the pandemic.
Feel free to share your best finds.
they're playing...
Hi,I am working on an algorithm which uses the following Bob Jenkins Hash. Below are the reference of Bob Jenkins:http://burtleburtle.net/bob/hash/evahash.html(https://burtleburtle.net/bob/c/lookup2.c)It...
Antenna Recommendation for Altera Nano De0
Started by 6 years ago●5 replies●latest reply 6 years ago●111 viewsHello friends,I am new in this forum. I have started doing my final project. I am going to do Software Defined Radio over FPGA. In this project I am using Altera...
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