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Expect Downtime

Started by stephaneb 2 years ago14 replieslatest reply 2 years ago196 views
Edit #1 01/19 10:12am: well, false start with the new host.  Their migration team was supposed to help me through the process this morning but I am not hearing...

Back online - Migration done

Started by stephaneb 2 years ago1 replylatest reply 2 years ago129 views
It looks like the migration went well.  I found a couple of errors but solved them quickly.  I will continue to do some testing to make sure that everything is...
I am trying to bring up the DE10 Nano kit that has Cyclone V FPGA using the open source Cascade compiler https://github.com/vmware/cascade from VMware. It uses Quartus...

timing analysis query

Started by dayana42200 2 years ago33 views
Hello everyone.Currently, Im designing a processing element.This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.I have problem...

LVDS as a comparator

Started by Tanu3 2 years ago85 views
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal...

VHDL : function not recognizing a type defined in package

Started by jmca 2 years ago1 replylatest reply 2 years ago110 views
Hi,I am trying to write a function that reads from csv file and formats data to fixed point so it can be used to initialize ROM contents.The function is contained...

HELP NEEDED - FPGA related Christmas present suggestions

Started by JB757 3 years ago1 replylatest reply 3 years ago54 views
Hi, I know nothing about FPGA, integrated circuits, electronics, et cetera. I do know that it's a field my father is interested in. A little background, he's worked...

ML310 board by Xilinx

Started by rbeekhuijzen 3 years ago5 replieslatest reply 3 years ago117 views
Recently I came into the possession of a ML310 (Virtex-II Pro) board made by Xilinx. IT is an old board and unfortunately, except for a few User Guides nothing can...

Lattice MIPI-CSI2 IP

Started by stanzanim 3 years ago103 views
Due to lack of support from lattice - and also mi lack of experiece with Lattice: I come from the xlinx world - I am here to get help about integrating this IP on...

Timing paths from wires to registers

Started by kaz 3 years ago3 replieslatest reply 3 years ago47 views
Hi All,I 've come across this case (please see figure below) .I have a synchronous system but four constants (A,B,C,D) are implemented on wires and any one of them...

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