Lattice MachXO2 Timing errors.

Started by SpiderKenny 1 year ago4 replieslatest reply 1 year ago145 views
I have a pretty simple verilog project, in Lattice Diamond 3.11.My top module instantiates an OSCH (Lattice IP library) oscillator at 133 mhz, and a 'ws2812b' module...


Started by Misiakoulis_dev 1 year ago55 views
Hi all, I have a PYNQ-Z1 FPGA and I want to make encryption on drone communication data. At this point I want to convert a standalone application (bare metal)...

Use of DAC in ZCU111 Dev Board

Started by nicolas05 1 year ago5 replieslatest reply 1 year ago148 views
Hello Forum! ,I am a beginner with FPGA's. I want to implement an analog square wave generator using a ZCU111 Dev Board, but experiences with other boards can...

Some doubt about reset bridge

Started by nori 2 years ago1 replylatest reply 1 year ago41 views
Hi Forum,I am referring to this circuit:As you know it is well known circuit for pre-synchronizing reset (reset bridge).Looking into small details I imagine violation...
Hi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(

I am new to FPGA, I need guidance to understand difference between UCF andXDC

Started by mekjayk 2 years ago2 replieslatest reply 2 years ago288 views
Hello everyone,I have kintex-7 based kit . I started learning about FPGA using udemy courses. where pin placement...

Reusing registers in VHDL FSM code

Started by darian16 2 years ago5 replieslatest reply 2 years ago87 views
Hello, I need to write a Finite State Machine (FSM) in VHDL code and  want to have several computations being processed at the same time (a standard pipeline)....
HiI have a zedboard and a nexys video artix 7 board. I am generating a sinusoid from DDS Core of the same frequency (by supplying the same phase increment and the...

Tips for using Xilinx Ultra RAMs

Started by weetabixharry 2 years ago2 replieslatest reply 2 years ago635 views
What are the main considerations that I should be aware of if I want to use Ultra RAMs in my design?I am familiar with the Block RAMs used in 5-, 6- and 7-series...

recovery/removal violations, does it always matter?

Started by kaz 2 years ago9 replieslatest reply 2 years ago275 views
Hi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...

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