FPGA curve fitting

Started by kiyoshi7 2 years ago14 replieslatest reply 2 years ago460 views
hey, I'll give a little background before I start, I've recently started with FPGA (I'm more used to PIC MCUs), which I'm planning to use with a high speed analog...

Reduce Phase of a filtered data set

Started by shaddoll 2 years ago3 replieslatest reply 2 years ago45 views
Hi :)So when you filter data sets using moving average, median or any other filter, they produce some kind of shift and they cant properly follow the original...

DSP Windowing function

Started by Bheki 2 years ago7 replieslatest reply 2 years ago238 views
Hi everyoneI am new in #FPGA programming, yet I have programming experience in using C, matlab, SQL, and other languages. I am assigned a task of creating a Windowing...

Unlimited display on the board

Started by jeepcoon 2 years ago2 replieslatest reply 2 years ago146 views
Hello everyone, I find a xilinx zynq single board computer Z-turn board, the price is attractive and I would like to order one for my evaluation. But I find it has...

FPGA - ML & DL

Started by jimmycarter 2 years ago2 replieslatest reply 2 years ago72 views
Hi I planning to do my research in Deep Learning in FPGA. Can you suggest any specific research topics within this fiels ? What is the scope of the field ?

Makefiles and FPGA projects

Started by Ptorru 2 years ago2 replieslatest reply 2 years ago103 views
Hi there,I am engineering a makefile based build system for FPGA based projects.I was considering making a blog entry with my challenges, solutions, and thoughts. Would...

Mounting a game On FPGA

Started by obenyaala 2 years ago6 replieslatest reply 2 years ago168 views
Hi, I don't know if I am allowed to ask this question, because it is complicated but I tried searching couldn't find anything that helped, so my question is stupid...

Effective schematic for GPIO pin

Started by l8rPIC 2 years ago1 replylatest reply 2 years ago113 views
I am working on a project using the cyclone V from Altera. The FPGA has 3.3v GPIO pins and I would like to know what I could use to mimic a GPIO pins output. I am...

Overloading assignment operator '<=' in vhdl

Started by LabPe43 2 years ago1 replylatest reply 2 years ago182 views
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DSP Filter Verification in FPGA

Started by srid 2 years ago30 replieslatest reply 2 years ago315 views
I am designing the FIR filter for up conversion in FPGA. Input to the FIR filter is 16 bits wide (-32768 to 32767) with the maximum co-eff value of 32767. This produces...

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