How to use non-dedicated IO pins as clock source to FPGA PLL or Clock MUX?I try to use "PROHIBIT PRIMARY" preference, as described in:TN1263 ECP5 and ECP5-5G sysCLOCK...

SPI core in EDK generates junk output

Started by shreeranjani 2 years ago42 views
Hi , I am working in Embedded Development Kit EDK 13.2 Virtex 5, on spi (one master one slave). Microblaze is operated at 50Mhz input clock. spi in edk is configured...

FT601Q: 245 Synchronous FIFO mode.

Started by atom1477 2 years ago1 replylatest reply 2 years ago120 views
Hi.I'm trying to use FT601Q with FPGA. But I have some loss of data. And I don't know if this is an error in my FPGA code, or an error in FT601Q chip. FT601Q have...

Lattice MachXO2 Timing errors.

Started by SpiderKenny 2 years ago4 replieslatest reply 2 years ago182 views
I have a pretty simple verilog project, in Lattice Diamond 3.11.My top module instantiates an OSCH (Lattice IP library) oscillator at 133 mhz, and a 'ws2812b' module...


Started by Misiakoulis_dev 2 years ago56 views
Hi all, I have a PYNQ-Z1 FPGA and I want to make encryption on drone communication data. At this point I want to convert a standalone application (bare metal)...

Use of DAC in ZCU111 Dev Board

Started by nicolas05 2 years ago5 replieslatest reply 2 years ago176 views
Hello Forum! ,I am a beginner with FPGA's. I want to implement an analog square wave generator using a ZCU111 Dev Board, but experiences with other boards can...

Some doubt about reset bridge

Started by nori 2 years ago1 replylatest reply 2 years ago44 views
Hi Forum,I am referring to this circuit:As you know it is well known circuit for pre-synchronizing reset (reset bridge).Looking into small details I imagine violation...
Hi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(

I am new to FPGA, I need guidance to understand difference between UCF andXDC

Started by mekjayk 2 years ago2 replieslatest reply 2 years ago348 views
Hello everyone,I have kintex-7 based kit . I started learning about FPGA using udemy courses. where pin placement...

Reusing registers in VHDL FSM code

Started by darian16 2 years ago5 replieslatest reply 2 years ago97 views
Hello, I need to write a Finite State Machine (FSM) in VHDL code and  want to have several computations being processed at the same time (a standard pipeline)....

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