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Block diagram software

Started by rnp 2 years ago11 replieslatest reply 2 years ago269 views
Hello everybody,I am searching for a WYSIWYG software to draw, from complex to simple, block diagrams for documenting my personal projects. So far I am using CircuiTikz...

OT: Laughing in the Face of Adversity

Started by stephaneb 2 years ago14 replieslatest reply 2 years ago331 views
Humor helps us take back control and to connect - two things we have lost in our fight against the pandemic. Feel free to share your best finds. they're playing...

Bob Jenkins Hash on FPGA

Started by Bobby29999 2 years ago5 replieslatest reply 2 years ago160 views
Hi,I am working on an algorithm which uses the following Bob Jenkins Hash. Below are the reference of Bob Jenkins:http://burtleburtle.net/bob/hash/evahash.html(https://burtleburtle.net/bob/c/lookup2.c)It...

Antenna Recommendation for Altera Nano De0

Started by furkankalayci 2 years ago5 replieslatest reply 2 years ago42 views
Hello friends,I am new in this forum. I have started doing my final project. I am going to do Software Defined Radio over FPGA. In this project I am using Altera...

Inverse Transform Sampling method on FPGA

Started by Bobby29999 2 years ago3 replieslatest reply 2 years ago40 views
Hi,I am working on pseudo random number generation topic. To be precise,  Inverse Transform Sampling method , i.e., a method for generating sample numbers...

Lattice FPGA timing constraint help

Started by dave94024 2 years ago4 replieslatest reply 2 years ago68 views
I have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior.  I'm pretty sure it's due to timing constraint issues...

Covid-19 Stories

Started by stephaneb 2 years ago21 replieslatest reply 2 years ago467 views
How about we share with each others the impact that the current pandemic is having on our lives & work?  I will start. First, I am located in Canada, where...

QSPI Slave controller IP core

Started by sachinwannabe 2 years ago2 replieslatest reply 2 years ago94 views
Hi,I can't seem to find a QSPI slave IP core. Any pointers? My application needs to interface with a QSPI master interface on a processor.Thanks
I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box on the HDMI...

Is this possible with an FPGA?

Started by Joe3502 2 years ago8 replieslatest reply 2 years ago65 views
Hi All, I am starting to learn Verilog in order to program FPGAs. I have a project where I need to take three digital signals coming from three hall sensors on...

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