I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1. It is the video example, which creates a blue box on the HDMI...

Hi All, I am starting to learn Verilog in order to program FPGAs. I have a project where I need to take three digital signals coming from three hall sensors on...

Hello,by now, I suspect that most of you are already signed-up for the upcoming Embedded Online Conference that I am currently organizing with Jacob Beningo (@beningjw).I...

Hi,I am an FPGA engineer in charge of developing a test application that must offload a continuous test data stream between host PC and a test hardware. I do not...

Together with my friend Jacob Beningo, we have been working hard lately on putting together a platform to hold online conferences:https://www.embeddedonlineconference.comBefore...

Hello,I implemented running sum filter In FPGA.  Input width(IW) is 8 and the log(based two) of the maximum number of averages(LGMEM) is 14. The output/accumulator...

Edit #1 01/19 10:12am: well, false start with the new host.  Their migration team was supposed to help me through the process this morning but I am not hearing...

It looks like the migration went well.  I found a couple of errors but solved them quickly.  I will continue to do some testing to make sure that everything is...

I am trying to bring up the DE10 Nano kit that has Cyclone V FPGA using the open source Cascade compiler https://github.com/vmware/cascade from VMware. It uses Quartus...

Hello everyone.Currently, Im designing a processing element.This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.I have problem...