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Quartus Prime Licensing

Started by Echoonezero 2 years ago1 replylatest reply 2 years ago216 views
Hello,I have the following questions:1. A Quartus Prime Lite version is sufficient for my FPGA design. Can I use only the Lite version in my company for commercial...

Libero SmartFusion 2 Pinout Chart

Started by cwible 2 years ago38 views
Hi everyone, I am trying to learn how to use the SmartFusion 2 Maker Kit for a research project. Right now I am trying to simply flash an LED but I cant find which...

Clock domain crossing

Started by vpsampath 2 years ago294 views
Constraints are essential when developing a new design. The constraints set up are the environmental, clock, test and power boundaries the designers must keep themselves...

Creating custom IP for zedboard

Started by shlomishab 2 years ago57 views
Hi all,I'm working on a video streming project with a zedboard and an ov7670 camera module. I found a similar project online, made by Mike Field, and I was able...

TinyFPGA BX Creating Two OR Gates

Started by Joe3502 3 years ago1 replylatest reply 2 years ago75 views
Hi all,  First off, I hope that you and your families are staying safe and well during this time of global pandemic.  I just received my TinyFPGA in the mail yesterday...
Hello everyone,I am migrating an old MAXPLUS II design to Quartus II. I could transfer the schematic files and the design is ready, but not able to migrate the...

Processing Gain at output of ADC

Started by rathnakarreddy 3 years ago2 replieslatest reply 3 years ago87 views
With adequate filtering after AD conversion, the SNR is calculated as,SNR=6.02*N+1.76+10*log(fs/(2*BW));N-> No: of ADC bitsThe term 10log(fs/2*BW) is referred...

How to avoid Blocking Statement in Verilog

Started by rathnakarreddy 3 years ago1 replylatest reply 3 years ago63 views
Hi,I have a matlab code and I have to convert it to verilog.The matlab code is as follows:/****************************************************************/clc;clear...

ADC SNR and Processing Gain

Started by rathnakarreddy 3 years ago3 replieslatest reply 3 years ago184 views
Hi,with reference to the following article,https://www.dsprelated.com/showthread/comp.dsp/727...I have understood that decimating doesn't destroy the processing...

How to make sure clock is from the main clock tree?

Started by andy92806 3 years ago6 replieslatest reply 3 years ago90 views
Let's say you have a module that needs a clock like this:module need_clk(i_clk, .....) input i_clk;. .......endmoduleAt the top level, you then have a statement...

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