Forums
I'd like to use Vivado in non-project mode, using makefiles and Tcl scripts. However, my chip is a Zynq-7000 SoC where Vivado needs to generate a module representing...
Started by Trying to solve the following contradiction about "set_multicycle_path"case 1: "Vivado using constraints" pdf states that for most cases of timing relaxing multicycle...
Hello guys,I have been trying to implement to implement the SHA256 algorithm on my ARTY A7 35t using VivadoI am using TeraTerm to send information to the board...
Doubt about constraining external input
Started by 3 years ago●4 replies●latest reply 3 years ago●117 viewsHi all,I am usig an AD9914 DDShttps://www.analog.com/media/en/technical-documentation/data-sheets/AD9914.pdfwith its DROVER output connected to a I/O of the FPGA...
Efficient implementation of FIR filters on a FPGA
Started by 3 years ago●2 replies●latest reply 3 years ago●121 viewsHello there,I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here: PS:I'd...
Polyphase Filter Bank channelizer issue
Started by 3 years ago●5 replies●latest reply 3 years ago●896 viewsHello, I am currently studying the implementation of a Polyphase Filter Bank channelizer designed by Xilinx in its XAPP1161. The architecture is composed by a single...
UART communication For Nexys A7-100t
Started by 3 years ago●1 reply●latest reply 3 years ago●881 viewsHello,I'm new to UART for FPGA and recently I tried a demo project that I found at: https://www.fpga4fun.com/SerialInterface.htmlMy problem is using RxD_data_ready...
I've been working on a video streaming project using a zedboard and the ov7670 camera. My project is based on this one (capture and vga .vhd files): https://www.hackster.io/dhq/fpga-camera-system-14d6ea...
Attempting to implement UART - Unexpected Behaviour
Started by 4 years ago●9 replies●latest reply 4 years ago●272 viewsI have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to implement the...
Modelsim Error: (vsim-3555) Identifier is not a unit name for the physical type
Started by 4 years ago●5 replies●latest reply 4 years ago●49 viewsHello,I am a newbie in verifying complex FPGA designs. In my testbench, I am reading the test vectors from a text file and assigning them to the input ports...
Please login (on the right) if you already have an account on this platform.
Otherwise, please use this form to register (free) an join one of the largest online community for Electrical/Embedded/DSP/FPGA/ML engineers:
