Vivado Tcl

Started by Kocsonya 3 years ago3 replieslatest reply 3 years ago247 views
I'd like to use Vivado in non-project mode, using makefiles and Tcl scripts. However, my chip is a Zynq-7000 SoC where Vivado needs to generate a module representing...

set multicycle path contradiction on hold value

Started by kaz 3 years ago421 views
Trying to solve the following contradiction about "set_multicycle_path"case 1: "Vivado using constraints" pdf states that for most cases of timing relaxing multicycle...

Sha256 on FPGA board

Started by Iani97 3 years ago119 views
Hello guys,I have been trying to implement to implement the SHA256 algorithm on my ARTY A7 35t using VivadoI am using TeraTerm to send information to the board...

Doubt about constraining external input

Started by simonzz 3 years ago4 replieslatest reply 3 years ago117 views
Hi all,I am usig an AD9914 DDShttps://www.analog.com/media/en/technical-documentation/data-sheets/AD9914.pdfwith its DROVER output connected to a I/O of the FPGA...

Efficient implementation of FIR filters on a FPGA

Started by DHMarinov 3 years ago2 replieslatest reply 3 years ago121 views
Hello there,I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here: PS:I'd...

Polyphase Filter Bank channelizer issue

Started by epetragl 3 years ago5 replieslatest reply 3 years ago913 views
Hello, I am currently studying the implementation of a Polyphase Filter Bank channelizer designed by Xilinx in its XAPP1161. The architecture is composed by a single...

UART communication For Nexys A7-100t

Started by MCU231 3 years ago1 replylatest reply 3 years ago917 views
Hello,I'm new to UART for FPGA and recently I tried a demo project that I found at: https://www.fpga4fun.com/SerialInterface.htmlMy problem is using RxD_data_ready...

Zedboard and the ov7670 settings

Started by shlomishab 4 years ago192 views
I've been working on a video streaming project using a zedboard and the ov7670 camera. My project is based on this one (capture and vga .vhd files): https://www.hackster.io/dhq/fpga-camera-system-14d6ea...

Attempting to implement UART - Unexpected Behaviour

Started by fayalalebrun 4 years ago9 replieslatest reply 4 years ago275 views
I have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to implement the...

Modelsim Error: (vsim-3555) Identifier is not a unit name for the physical type

Started by Echoonezero 4 years ago5 replieslatest reply 4 years ago49 views
Hello,I am a newbie in verifying complex FPGA designs.  In my testbench, I am reading the test vectors from  a text file and assigning them to the input ports...

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