replacement for XILINX XC3020A-7PC84C

Started by hamed_vrz 8 months ago3 replieslatest reply 8 months ago47 views
Hi Guys,I'm looking for an similar FPGA with XILINX XC3020A-7PC84C to replace with it.i want to do this replacement with minimum changes in circuit design.I checked...

Virtual (cycle accurate) CPU simulations

Started by strubi 8 months ago3 replieslatest reply 8 months ago104 views
Hi all, I've been hacking away on a CPU builder in the past years that allows to build a microcontroller kinda from scratch with some standard peripherals in...

MachXO2 I2C configuration. EFB I2C block synthesis error.

Started by atom1477 8 months ago2 replieslatest reply 8 months ago63 views
Hello.I creating project with LCMXO2-1200HC device in QFN32 package, so i have very limited number of IO pins and I want to configuring FPGA by I2C instead of JTAG.I...

How to understand -edge option if first edge of generated clock is falling edge?

Started by tip_can19 9 months ago1 replylatest reply 9 months ago40 views
I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like below:I...

What would be difference between clock latency and propagation delay?

Started by tip_can19 9 months ago4 replieslatest reply 9 months ago107 views
I believe the clock latency is the total time it takes from the clock source to an end point. Whereas, the propagation delay would simply be the delay between...

Activating CH7301 on SP605 board #xilinx #vhdl

Started by ajellis 10 months ago2 replieslatest reply 10 months ago109 views
HelloI am working on a project using the SP605 for a video application. Currently I'm trying to output a picture via the DVI output which is driven by a CH7301...

remains a black box sine it has not binding entity

Started by ajellis 11 months ago7 replieslatest reply 11 months ago247 views
HI I'm working on a design where I have implemented an I2C module which I'm trying to use as a component in another piece of VHDL. The problem I've got is that...

A Law compression for FPGA

Started by kaz 11 months ago7 replieslatest reply 11 months ago74 views
Hi all,Referring to this doc on A law compression (table 1): table is meant for 13 bits signed to 8 bits...

Lattice: Utilization and Clock Report

Started by cubosubtil 12 months ago3 replieslatest reply 11 months ago36 views
Hello,I have only one clock in my design and the number of clock load in my clock report(.par) does not correspond to the number of the registers in the map report(.mrp),...

simple line drive generator doesn't work properly

Started by ombz 11 months ago3 replieslatest reply 11 months ago33 views
Hi guysI don't have any real-world experience with synthesizable VHDL and FPGA's but I've been really curious about it for a long time. So I've found an old experimenter's...

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