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LVDS as a comparator

Started by Tanu3 1 year ago56 views
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal...

VHDL : function not recognizing a type defined in package

Started by jmca 1 year ago1 replylatest reply 1 year ago41 views
Hi,I am trying to write a function that reads from csv file and formats data to fixed point so it can be used to initialize ROM contents.The function is contained...

HELP NEEDED - FPGA related Christmas present suggestions

Started by JB757 1 year ago1 replylatest reply 1 year ago43 views
Hi, I know nothing about FPGA, integrated circuits, electronics, et cetera. I do know that it's a field my father is interested in. A little background, he's worked...

DueProLogic by EarthPeopleTechnology: Help making it work?

Started by AwesomeCronk 1 year ago5 replieslatest reply 1 year ago74 views
I was given a DueProLogic(DPL) board last year as a birthday gift. I never could get it to work. After having built my desktop and having installed Quartus and the...

ML310 board by Xilinx

Started by rbeekhuijzen 1 year ago5 replieslatest reply 1 year ago72 views
Recently I came into the possession of a ML310 (Virtex-II Pro) board made by Xilinx. IT is an old board and unfortunately, except for a few User Guides nothing can...

Lattice MIPI-CSI2 IP

Started by stanzanim 1 year ago63 views
Due to lack of support from lattice - and also mi lack of experiece with Lattice: I come from the xlinx world - I am here to get help about integrating this IP on...

Timing paths from wires to registers

Started by kaz 1 year ago3 replieslatest reply 1 year ago36 views
Hi All,I 've come across this case (please see figure below) .I have a synchronous system but four constants (A,B,C,D) are implemented on wires and any one of them...
How to use non-dedicated IO pins as clock source to FPGA PLL or Clock MUX?I try to use "PROHIBIT PRIMARY" preference, as described in:TN1263 ECP5 and ECP5-5G sysCLOCK...

SPI core in EDK generates junk output

Started by shreeranjani 1 year ago39 views
Hi , I am working in Embedded Development Kit EDK 13.2 Virtex 5, on spi (one master one slave). Microblaze is operated at 50Mhz input clock. spi in edk is configured...

FT601Q: 245 Synchronous FIFO mode.

Started by atom1477 1 year ago1 replylatest reply 1 year ago102 views
Hi.I'm trying to use FT601Q with FPGA. But I have some loss of data. And I don't know if this is an error in my FPGA code, or an error in FT601Q chip. FT601Q have...

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