Lattice MIPI-CSI2 IP

Started by stanzanim 11 months ago59 views
Due to lack of support from lattice - and also mi lack of experiece with Lattice: I come from the xlinx world - I am here to get help about integrating this IP on...

Timing paths from wires to registers

Started by kaz 11 months ago3 replieslatest reply 11 months ago33 views
Hi All,I 've come across this case (please see figure below) .I have a synchronous system but four constants (A,B,C,D) are implemented on wires and any one of them...
How to use non-dedicated IO pins as clock source to FPGA PLL or Clock MUX?I try to use "PROHIBIT PRIMARY" preference, as described in:TN1263 ECP5 and ECP5-5G sysCLOCK...

SPI core in EDK generates junk output

Started by shreeranjani 1 year ago37 views
Hi , I am working in Embedded Development Kit EDK 13.2 Virtex 5, on spi (one master one slave). Microblaze is operated at 50Mhz input clock. spi in edk is configured...

FT601Q: 245 Synchronous FIFO mode.

Started by atom1477 1 year ago1 replylatest reply 1 year ago85 views
Hi.I'm trying to use FT601Q with FPGA. But I have some loss of data. And I don't know if this is an error in my FPGA code, or an error in FT601Q chip. FT601Q have...

Lattice MachXO2 Timing errors.

Started by SpiderKenny 1 year ago4 replieslatest reply 1 year ago119 views
I have a pretty simple verilog project, in Lattice Diamond 3.11.My top module instantiates an OSCH (Lattice IP library) oscillator at 133 mhz, and a 'ws2812b' module...


Started by Misiakoulis_dev 1 year ago54 views
Hi all, I have a PYNQ-Z1 FPGA and I want to make encryption on drone communication data. At this point I want to convert a standalone application (bare metal)...

Use of DAC in ZCU111 Dev Board

Started by nicolas05 1 year ago5 replieslatest reply 1 year ago129 views
Hello Forum! ,I am a beginner with FPGA's. I want to implement an analog square wave generator using a ZCU111 Dev Board, but experiences with other boards can...

Some doubt about reset bridge

Started by nori 1 year ago1 replylatest reply 1 year ago39 views
Hi Forum,I am referring to this circuit:As you know it is well known circuit for pre-synchronizing reset (reset bridge).Looking into small details I imagine violation...
Hi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(

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