Final Push and Could use your Help

Started by stephaneb 2 years ago192 views
Hello,by now, I suspect that most of you are already signed-up for the upcoming Embedded Online Conference that I am currently organizing with Jacob Beningo (@beningjw).I...

UDP or TCP/IP FPGA solution for max streaming rate of 640 Mbps

Started by jmca 2 years ago6 replieslatest reply 2 years ago189 views
Hi,I am an FPGA engineer in charge of developing a test application that must offload a continuous test data stream between host PC and a test hardware. I do not...

New Embedded Online Conference website, need your help testing it.

Started by stephaneb 2 years ago15 replieslatest reply 2 years ago206 views
Together with my friend Jacob Beningo, we have been working hard lately on putting together a platform to hold online conferences:https://www.embeddedonlineconference.comBefore...

Running Sum filter

Started by Adira 2 years ago17 replieslatest reply 2 years ago317 views
Hello,I implemented running sum filter In FPGA.  Input width(IW) is 8 and the log(based two) of the maximum number of averages(LGMEM) is 14. The output/accumulator...

Expect Downtime

Started by stephaneb 2 years ago14 replieslatest reply 2 years ago187 views
Edit #1 01/19 10:12am: well, false start with the new host.  Their migration team was supposed to help me through the process this morning but I am not hearing...

Back online - Migration done

Started by stephaneb 2 years ago1 replylatest reply 2 years ago124 views
It looks like the migration went well.  I found a couple of errors but solved them quickly.  I will continue to do some testing to make sure that everything is...
I am trying to bring up the DE10 Nano kit that has Cyclone V FPGA using the open source Cascade compiler from VMware. It uses Quartus...

timing analysis query

Started by dayana42200 2 years ago32 views
Hello everyone.Currently, Im designing a processing element.This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.I have problem...

LVDS as a comparator

Started by Tanu3 2 years ago79 views
I interfaced FPGA(Kintex_7, LVDS_25, Vadj=1.8v)with external board to provide inputs(Analog voltage and reference voltage) to LVDS. I adjusted frequencies of signal...

VHDL : function not recognizing a type defined in package

Started by jmca 2 years ago1 replylatest reply 2 years ago76 views
Hi,I am trying to write a function that reads from csv file and formats data to fixed point so it can be used to initialize ROM contents.The function is contained...

Registering will allow you to participate to the forums on ALL the related sites and give you access to all pdf downloads.

Sign up

I agree with the terms of use and privacy policy.

Try our occasional but popular newsletter. VERY easy to unsubscribe.
or Sign in