Doubt about constraining external input

Started by simonzz 2 years ago4 replieslatest reply 2 years ago74 views
Hi all,I am usig an AD9914 DDS its DROVER output connected to a I/O of the FPGA...

Implementing a folded FIR on FPGA

Started by DHMarinov 2 years ago2 replieslatest reply 2 years ago76 views
Hello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...

Efficient implementation of FIR filters on a FPGA

Started by DHMarinov 2 years ago2 replieslatest reply 2 years ago101 views
Hello there,I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here: PS:I'd...

Xilinx FIR Compiler Fractional Rate Converter

Started by ismailt42 2 years ago1 replylatest reply 2 years ago75 views
Hello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...

Polyphase Filter Bank channelizer issue

Started by epetragl 2 years ago5 replieslatest reply 2 years ago605 views
Hello, I am currently studying the implementation of a Polyphase Filter Bank channelizer designed by Xilinx in its XAPP1161. The architecture is composed by a single...

UART communication For Nexys A7-100t

Started by MCU231 2 years ago1 replylatest reply 2 years ago407 views
Hello,I'm new to UART for FPGA and recently I tried a demo project that I found at: problem is using RxD_data_ready...

Zedboard and the ov7670 settings

Started by shlomishab 2 years ago135 views
I've been working on a video streaming project using a zedboard and the ov7670 camera. My project is based on this one (capture and vga .vhd files):

Attempting to implement UART - Unexpected Behaviour

Started by fayalalebrun 2 years ago9 replieslatest reply 2 years ago165 views
I have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to implement the...

Modelsim Error: (vsim-3555) Identifier is not a unit name for the physical type

Started by Echoonezero 2 years ago5 replieslatest reply 2 years ago33 views
Hello,I am a newbie in verifying complex FPGA designs.  In my testbench, I am reading the test vectors from  a text file and assigning them to the input ports...

Will this FPGA be suitable for DSP purposes?

Started by corn1996 2 years ago8 replieslatest reply 2 years ago353 views
Hey guys! My masters degree thesis is digital lock-in amplifier. I want to make it on an FPGA to learn this piece of hardware. Basically I have a budget of 220€...

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