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I need a SERDES with a built in ADC and DAC. I am skeptical about 2 boards here, the ULX3S and ECP5 Evaluation board. The former can supposedly be programmed...
Which FPGA brand is industry standard for defense and radio/radar market?

Greetings, I have a small company that works in the defense and telecommunications sector. In the coming months we have to train some of our engineers to...
Hi all,I got an FPGA design running #FFT at 256 points. Our system requires fft be configured as either 256 or 512 points on the run. I can use variable fft that...
Deep-learning FPGA. How did you?

Maybe I'm one of the worst people to be learning FPGAs because I've been a firmware developer on embedded CPUs and an application developer on Mac / Windows for...
Hello, I am new to FPGA. I have seen a template in DE0-nano. I would like to display the value in "PWM_width <= PWM_width[5:0]+ PWM_adj;" one by one in a screen...
I have Nexys4 FPGA , it has a system clock of 100mhz, can it generate 200mhz clock, when using Clocking Wizard IP?
DueProLogic by EarthPeopleTechnology: Help making it work?

I was given a DueProLogic(DPL) board last year as a birthday gift. I never could get it to work. After having built my desktop and having installed Quartus and the...
I'd like to use Vivado in non-project mode, using makefiles and Tcl scripts. However, my chip is a Zynq-7000 SoC where Vivado needs to generate a module representing...
Trying to solve the following contradiction about "set_multicycle_path"case 1: "Vivado using constraints" pdf states that for most cases of timing relaxing multicycle...
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