FPGARelated.com
Forums

DE0-nano cannot read multi-sensors in parallel

Started by Roy_WCH 1 year ago4 replieslatest reply 1 year ago31 views
Hello. I have purchased DE0-nano (Terasic). I plug two sensors into the ADC system, but it needs to change the switch (or pin) in order to read another sensor....

Installing a license to run MicroChip MicroSemi Libero

Started by carstenherr 1 year ago1 replylatest reply 1 year ago55 views
I am in the process of evaluating vendors and FPGAs for a security project and had been pointed to also MicroChip and the Libero Suite. The main task is to get a...
In a project I'm working on an FPGA, I'm converting a 48-bit MAC address to 16-bit using the Hash algorithm. RAM size is 2^16 bits and I have 8 ETHERNET ports. I...

Connecting Nanoboard 3000 to Xilinx ISE

Started by Biggie 2 years ago44 views
I am trying to connect my nanoboard 3000 with Spartan 3AN to Impact. I have added the correct .bsd file and used a Xilinx Platform Cable - https://www.waveshare.com/w/upload/d/d6/XILINX_Pla......

ULX3S vs ECP5 Evaluation Board

Started by Aishwarya0210 2 years ago32 views
Hi! I need a SERDES with a built in ADC and DAC. I am skeptical about 2 boards here, the ULX3S and ECP5 Evaluation board. The former can supposedly be programmed...

Which FPGA brand is industry standard for defense and radio/radar market?

Started by federicomassimi 2 years ago2 replieslatest reply 2 years ago76 views
Greetings,     I have a small company that works in the defense and telecommunications sector. In the coming months we have to train some of our engineers to...

fft combinations

Started by kaz 8 years ago18 replieslatest reply 2 years ago813 views
Hi all,I got an FPGA design running #FFT at 256 points. Our system requires fft be configured as either 256 or 512 points on the run. I can use variable fft that...

Deep-learning FPGA. How did you?

Started by SpiderKenny 2 years ago6 replieslatest reply 2 years ago126 views
Maybe I'm one of the worst people to be learning FPGAs because I've been a firmware developer on embedded CPUs and an application developer on Mac / Windows for...

cout in FPGA

Started by WCH 2 years ago1 replylatest reply 2 years ago87 views
Hello, I am new to FPGA. I have seen a template in DE0-nano. I would like to display the value in "PWM_width <= PWM_width[5:0]+ PWM_adj;" one by one in a screen...

FPGA Clocking

Started by HGola 2 years ago3 replieslatest reply 2 years ago101 views
I have Nexys4 FPGA , it has a system clock of 100mhz, can it generate 200mhz clock, when using Clocking Wizard IP?

Please login (on the right) if you already have an account on this platform.

Otherwise, please use this form to register (free) an join one of the largest online community for Electrical/Embedded/DSP/FPGA/ML engineers: