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replacement for XILINX XC3020A-7PC84C
Started by 6 months ago●3 replies●latest reply 6 months ago●44 viewsHi Guys,I'm looking for an similar FPGA with XILINX XC3020A-7PC84C to replace with it.i want to do this replacement with minimum changes in circuit design.I checked...
Virtual (cycle accurate) CPU simulations
Started by 6 months ago●3 replies●latest reply 6 months ago●98 viewsHi all,
I've been hacking away on a CPU builder in the past years that allows to build a microcontroller kinda from scratch with some standard peripherals in...
MachXO2 I2C configuration. EFB I2C block synthesis error.
Started by 6 months ago●2 replies●latest reply 6 months ago●53 viewsHello.I creating project with LCMXO2-1200HC device in QFN32 package, so i have very limited number of IO pins and I want to configuring FPGA by I2C instead of JTAG.I...
How to understand -edge option if first edge of generated clock is falling edge?
Started by 7 months ago●1 reply●latest reply 7 months ago●36 viewsI am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like below:I...
What would be difference between clock latency and propagation delay?
Started by 7 months ago●4 replies●latest reply 7 months ago●101 viewsI believe the clock
latency is the total time it takes from the clock source to an end point.
Whereas, the
propagation delay would simply be the delay between...
Activating CH7301 on SP605 board #xilinx #vhdl
Started by 8 months ago●2 replies●latest reply 8 months ago●91 viewsHelloI am working on a project using the SP605 for a video
application. Currently I'm trying to output a picture via the DVI output
which is driven by a CH7301...
remains a black box sine it has not binding entity
Started by 9 months ago●7 replies●latest reply 9 months ago●219 viewsHI
I'm working on a design where I have implemented an I2C module which I'm trying to use as a component in another piece of VHDL.
The problem I've got is that...
Hi all,Referring to this doc on A law compression (table 1):http://www.young-engineering.com/docs/YoungEnginee...The table is meant for 13 bits signed to 8 bits...
Lattice: Utilization and Clock Report
Started by 10 months ago●3 replies●latest reply 9 months ago●33 viewsHello,I have only one clock in my design and the number of clock load in my clock report(.par) does not correspond to the number of the registers in the map report(.mrp),...
simple line drive generator doesn't work properly
Started by 9 months ago●3 replies●latest reply 9 months ago●32 viewsHi guysI don't have any real-world experience with synthesizable VHDL and FPGA's but I've been really curious about it for a long time. So I've found an old experimenter's...
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