Hi Forum,I am referring to this circuit:As you know it is well known circuit for pre-synchronizing reset (reset bridge).Looking into small details I imagine violation...

Hi All,I have nine 8-bit values that I want to add using the dsp slices.As an example I tried this code from the Xilinx answer records(https://www.xilinx.com/support/answers/66429.html).I...

Hello everyone,I have kintex-7 based kit https://www.avnet.com/shop/us/products/xilinx/ek-k... . I started learning about FPGA using udemy courses. where pin placement...

Hello, I need to write a Finite State Machine (FSM) in VHDL code and  want to have several computations being processed at the same time (a standard pipeline)....

HiI have a zedboard and a nexys video artix 7 board. I am generating a sinusoid from DDS Core of the same frequency (by supplying the same phase increment and the...

What are the main considerations that I should be aware of if I want to use Ultra RAMs in my design?I am familiar with the Block RAMs used in 5-, 6- and 7-series...

Hi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...

Hi,I am working on a digital down conversion module for a project of mine. The module down converts a  signal at IF 455 KHz received through an ADC, multiplies...

Hi everyone,As part of a large FPGA/DSP project, I built a c extension library for python that mimicks the vhdl standard library fixed point functionality (https://github.com/smlgit/fpbinary)....

hi all !I am doing a BER (BIT ERROR RATE) in vhdl and I have to put 2 registers clear on read which counts the number of words in error and the number of bits...