Forums

Does anyone have experience in RFSoCs?

Started by amitjonak 9 months ago10 replieslatest reply 8 months ago125 views
Hello everyone!Our lab has bought the Xilinx ZCU1275 RFSoC and we, being Masters students are finding it extremely difficult to learn how to control the board. Since...

How to Interface LCD Text Module to FPGA

Started by johnkk89 9 months ago48 views
Hi, I'm taking an electronics class for college and I am very behind because of some family issues that I've been dealing with. I need to pass this class to graduate. I...

Block diagram software

Started by rnp 9 months ago11 replieslatest reply 9 months ago197 views
Hello everybody,I am searching for a WYSIWYG software to draw, from complex to simple, block diagrams for documenting my personal projects. So far I am using CircuiTikz...

OT: Laughing in the Face of Adversity

Started by stephaneb 10 months ago14 replieslatest reply 9 months ago300 views
Humor helps us take back control and to connect - two things we have lost in our fight against the pandemic. Feel free to share your best finds. they're playing...

Bob Jenkins Hash on FPGA

Started by Bobby29999 9 months ago5 replieslatest reply 9 months ago92 views
Hi,I am working on an algorithm which uses the following Bob Jenkins Hash. Below are the reference of Bob Jenkins:http://burtleburtle.net/bob/hash/evahash.html(https://burtleburtle.net/bob/c/lookup2.c)It...

Antenna Recommendation for Altera Nano De0

Started by furkankalayci 10 months ago5 replieslatest reply 9 months ago34 views
Hello friends,I am new in this forum. I have started doing my final project. I am going to do Software Defined Radio over FPGA. In this project I am using Altera...

Inverse Transform Sampling method on FPGA

Started by Bobby29999 10 months ago3 replieslatest reply 9 months ago34 views
Hi,I am working on pseudo random number generation topic. To be precise,  Inverse Transform Sampling method , i.e., a method for generating sample numbers...

Lattice FPGA timing constraint help

Started by dave94024 10 months ago4 replieslatest reply 10 months ago25 views
I have an application using a Lattice UltraPlus FPGA which is mostly working except for some marginal behavior.  I'm pretty sure it's due to timing constraint issues...

Covid-19 Stories

Started by stephaneb 10 months ago21 replieslatest reply 10 months ago430 views
How about we share with each others the impact that the current pandemic is having on our lives & work?  I will start. First, I am located in Canada, where...

QSPI Slave controller IP core

Started by sachinwannabe 10 months ago2 replieslatest reply 10 months ago53 views
Hi,I can't seem to find a QSPI slave IP core. Any pointers? My application needs to interface with a QSPI master interface on a processor.Thanks

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