Synchronizing clock cycles of FPGA in Mojo V3 with the clock cycle of a signal generator

Started by embeddedelectronics 8 months ago4 replieslatest reply 8 months ago94 views
Hi, So I want to synchronize the clock cycle of an FPGA in mojo V3 development board, whose default clock cycle is 50 MHz with a function generator. Currently,...

BRAM based FIFO

Started by maha_66 8 months ago3 replieslatest reply 8 months ago181 views
Hello! I am currently working on a matrix multiplication project. After performing the multiplication of the matrices, I am trying to build a module that can write...

VHDL Matrix Multiplication using UART and BRAM

Started by maha_66 9 months ago2 replieslatest reply 9 months ago123 views
My project involves performing matrix multiplication in vhdl. The two input matrices (8 bits each) are sent using a terminal and received via UART Rx. The FPGA...

Implementing octave algorithm in FPGA using c++

Started by Abhinav90 9 months ago11 replieslatest reply 9 months ago295 views
I am currently working on writing a scrambler and DeScrambler code for Orthogonal Frequency Division Multiplexing(OFDM). I am planning to write an algorithm for...

Searching for info about very old FPGA devices

Started by rodrigomelo9 10 months ago3 replieslatest reply 10 months ago67 views
Hello. My name is Rodrigo and I am from Argentina. I was looking for very old datasheets without success :-( (I searched a lot in google, archive.org, alldatasheets,...

HDL to Schematic Reporting

Started by Sanram 10 months ago5 replieslatest reply 10 months ago112 views
I am looking at a tool (or combination of tools) to perform the following. Please advise.1) Read Verilog/VHDL RTL input code and convert it to technology independent...

Mux versus internal high impledance

Started by prashantpd 10 months ago5 replieslatest reply 10 months ago61 views
Hi, I have been an FPGA designer for more than a decade now and tutor a class on FPGA design at University presently. In all these years, I have had two ways of...

Is an ACM subscription worthwhile?

Started by david_days 11 months ago2 replieslatest reply 10 months ago42 views
This morning on my codeproject.com feed, I got a link to an ACM article about C.  But what caught my eye was that the cover of the edition had an article about...

Writing 16-bit data to bram

Started by gundamz2001 11 months ago6 replieslatest reply 11 months ago128 views
Hello,I am currently working on a Xilinx development board that has PowerPC and virtex 5. I used Xilinx core generator to instantiate a bram with data width size...

Xilinx IPs for DFT, FFT, LTE_FFT

Started by kaz 11 months ago4 replieslatest reply 11 months ago76 views
Just started looking into Xilinx Fourier transform ip and found out that there are three versions:DFT: apparently useful for any resolutionFFT: power of 2 resolution,...

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