ULX3S vs ECP5 Evaluation Board

Started by Aishwarya0210 6 months ago30 views
Hi! I need a SERDES with a built in ADC and DAC. I am skeptical about 2 boards here, the ULX3S and ECP5 Evaluation board. The former can supposedly be programmed...

Which FPGA brand is industry standard for defense and radio/radar market?

Started by federicomassimi 7 months ago2 replieslatest reply 7 months ago65 views
Greetings,     I have a small company that works in the defense and telecommunications sector. In the coming months we have to train some of our engineers to...

fft combinations

Started by kaz 7 years ago18 replieslatest reply 11 months ago656 views
Hi all,I got an FPGA design running #FFT at 256 points. Our system requires fft be configured as either 256 or 512 points on the run. I can use variable fft that...

Deep-learning FPGA. How did you?

Started by SpiderKenny 12 months ago6 replieslatest reply 11 months ago98 views
Maybe I'm one of the worst people to be learning FPGAs because I've been a firmware developer on embedded CPUs and an application developer on Mac / Windows for...

cout in FPGA

Started by WCH 1 year ago1 replylatest reply 12 months ago69 views
Hello, I am new to FPGA. I have seen a template in DE0-nano. I would like to display the value in "PWM_width <= PWM_width[5:0]+ PWM_adj;" one by one in a screen...

FPGA Clocking

Started by HGola 1 year ago3 replieslatest reply 1 year ago78 views
I have Nexys4 FPGA , it has a system clock of 100mhz, can it generate 200mhz clock, when using Clocking Wizard IP?

DueProLogic by EarthPeopleTechnology: Help making it work?

Started by AwesomeCronk 3 years ago5 replieslatest reply 1 year ago152 views
I was given a DueProLogic(DPL) board last year as a birthday gift. I never could get it to work. After having built my desktop and having installed Quartus and the...

Vivado Tcl

Started by Kocsonya 2 years ago3 replieslatest reply 2 years ago148 views
I'd like to use Vivado in non-project mode, using makefiles and Tcl scripts. However, my chip is a Zynq-7000 SoC where Vivado needs to generate a module representing...

set multicycle path contradiction on hold value

Started by kaz 2 years ago237 views
Trying to solve the following contradiction about "set_multicycle_path"case 1: "Vivado using constraints" pdf states that for most cases of timing relaxing multicycle...

Sha256 on FPGA board

Started by Iani97 2 years ago107 views
Hello guys,I have been trying to implement to implement the SHA256 algorithm on my ARTY A7 35t using VivadoI am using TeraTerm to send information to the board...

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