Forums

Attempting to implement UART - Unexpected Behaviour

Started by fayalalebrun 2 years ago9 replieslatest reply 2 years ago142 views
I have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to implement the...

Modelsim Error: (vsim-3555) Identifier is not a unit name for the physical type

Started by Echoonezero 2 years ago5 replieslatest reply 2 years ago30 views
Hello,I am a newbie in verifying complex FPGA designs.  In my testbench, I am reading the test vectors from  a text file and assigning them to the input ports...

Will this FPGA be suitable for DSP purposes?

Started by corn1996 2 years ago8 replieslatest reply 2 years ago301 views
Hey guys! My masters degree thesis is digital lock-in amplifier. I want to make it on an FPGA to learn this piece of hardware. Basically I have a budget of 220€...

Quartus Prime Licensing

Started by Echoonezero 2 years ago1 replylatest reply 2 years ago112 views
Hello,I have the following questions:1. A Quartus Prime Lite version is sufficient for my FPGA design. Can I use only the Lite version in my company for commercial...

Libero SmartFusion 2 Pinout Chart

Started by cwible 2 years ago35 views
Hi everyone, I am trying to learn how to use the SmartFusion 2 Maker Kit for a research project. Right now I am trying to simply flash an LED but I cant find which...

Clock domain crossing

Started by vpsampath 2 years ago206 views
Constraints are essential when developing a new design. The constraints set up are the environmental, clock, test and power boundaries the designers must keep themselves...

Creating custom IP for zedboard

Started by shlomishab 2 years ago51 views
Hi all,I'm working on a video streming project with a zedboard and an ov7670 camera module. I found a similar project online, made by Mike Field, and I was able...

TinyFPGA BX Creating Two OR Gates

Started by Joe3502 2 years ago1 replylatest reply 2 years ago68 views
Hi all,  First off, I hope that you and your families are staying safe and well during this time of global pandemic.  I just received my TinyFPGA in the mail yesterday...
Hello everyone,I am migrating an old MAXPLUS II design to Quartus II. I could transfer the schematic files and the design is ready, but not able to migrate the...

Processing Gain at output of ADC

Started by rathnakarreddy 2 years ago2 replieslatest reply 2 years ago82 views
With adequate filtering after AD conversion, the SNR is calculated as,SNR=6.02*N+1.76+10*log(fs/(2*BW));N-> No: of ADC bitsThe term 10log(fs/2*BW) is referred...

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