Hi all,I'm working on a video streming project with a zedboard and an ov7670 camera module. I found a similar project online, made by Mike Field, and I was able...

Hi all,  First off, I hope that you and your families are staying safe and well during this time of global pandemic.  I just received my TinyFPGA in the mail yesterday...

Hello everyone,I am migrating an old MAXPLUS II design to Quartus II. I could transfer the schematic files and the design is ready, but not able to migrate the...

With adequate filtering after AD conversion, the SNR is calculated as,SNR=6.02*N+1.76+10*log(fs/(2*BW));N-> No: of ADC bitsThe term 10log(fs/2*BW) is referred...

Hi,I have a matlab code and I have to convert it to verilog.The matlab code is as follows:/****************************************************************/clc;clear...

Hi,with reference to the following article,https://www.dsprelated.com/showthread/comp.dsp/727...I have understood that decimating doesn't destroy the processing...

Let's say you have a module that needs a clock like this:module need_clk(i_clk, .....) input i_clk;. .......endmoduleAt the top level, you then have a statement...

Hi. I've seen other post like this on the forum, but it is still not clear to me so I will ask. Sorry if it seems like a repost.I'm creating an FFT/IFFT in verilog...

Hello everyone!Our lab has bought the Xilinx ZCU1275 RFSoC and we, being Masters students are finding it extremely difficult to learn how to control the board. Since...

Hi, I'm taking an electronics class for college and I am very behind because of some family issues that I've been dealing with. I need to pass this class to graduate. I...