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Doubt about constraining external input
Started by 2 years ago●4 replies●latest reply 2 years ago●74 viewsHi all,I am usig an AD9914 DDShttps://www.analog.com/media/en/technical-documentation/data-sheets/AD9914.pdfwith its DROVER output connected to a I/O of the FPGA...
Hello there,This is a follow up video about FIR filter design on FPGA. It goes into the implementation of a folded FIR as well as some aspects the design.You can...
Efficient implementation of FIR filters on a FPGA
Started by 2 years ago●2 replies●latest reply 2 years ago●101 viewsHello there,I made a short video in which I present a way to implement FIR filters on FPGA (Xilinx) by using only DSP slices. You can check it out here: PS:I'd...
Xilinx FIR Compiler Fractional Rate Converter
Started by 2 years ago●1 reply●latest reply 2 years ago●75 viewsHello, I have designed a FIR Fractional Rate Converter Filter by using FIR Compiler. The purpose of the design convert 20MHz(20M samples) to 20.48MHz(20.48M samples)...
Polyphase Filter Bank channelizer issue
Started by 2 years ago●5 replies●latest reply 2 years ago●605 viewsHello, I am currently studying the implementation of a Polyphase Filter Bank channelizer designed by Xilinx in its XAPP1161. The architecture is composed by a single...
UART communication For Nexys A7-100t
Started by 2 years ago●1 reply●latest reply 2 years ago●407 viewsHello,I'm new to UART for FPGA and recently I tried a demo project that I found at: https://www.fpga4fun.com/SerialInterface.htmlMy problem is using RxD_data_ready...
I've been working on a video streaming project using a zedboard and the ov7670 camera. My project is based on this one (capture and vga .vhd files): https://www.hackster.io/dhq/fpga-camera-system-14d6ea...
Attempting to implement UART - Unexpected Behaviour
Started by 2 years ago●9 replies●latest reply 2 years ago●165 viewsI have been trying to implement a UART in order to communicate between my Lattice MachXO3D board and my computer. At the moment I am attempting to implement the...
Modelsim Error: (vsim-3555) Identifier is not a unit name for the physical type
Started by 2 years ago●5 replies●latest reply 2 years ago●33 viewsHello,I am a newbie in verifying complex FPGA designs. In my testbench, I am reading the test vectors from a text file and assigning them to the input ports...
Will this FPGA be suitable for DSP purposes?
Started by 2 years ago●8 replies●latest reply 2 years ago●353 viewsHey guys! My masters degree thesis is digital lock-in amplifier. I want to make it on an FPGA to learn this piece of hardware. Basically I have a budget of 220€...
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