Forums Update, Tips and Tricks - Please Read!

Started by stephaneb 6 years ago13 replieslatest reply 1 month ago1936 views
It's been a few months since the launch of the new forums.  Here are a few thoughts. The thumbsup and beer buttons    If there is one thing that could have a...

fft combinations

Started by kaz 6 years ago18 replieslatest reply 4 weeks ago558 views
Hi all,I got an FPGA design running #FFT at 256 points. Our system requires fft be configured as either 256 or 512 points on the run. I can use variable fft that...

Deep-learning FPGA. How did you?

Started by SpiderKenny 2 months ago6 replieslatest reply 1 month ago61 views
Maybe I'm one of the worst people to be learning FPGAs because I've been a firmware developer on embedded CPUs and an application developer on Mac / Windows for...

cout in FPGA

Started by WCH 3 months ago1 replylatest reply 2 months ago46 views
Hello, I am new to FPGA. I have seen a template in DE0-nano. I would like to display the value in "PWM_width <= PWM_width[5:0]+ PWM_adj;" one by one in a screen...

FPGA Clocking

Started by HGola 3 months ago3 replieslatest reply 3 months ago68 views
I have Nexys4 FPGA , it has a system clock of 100mhz, can it generate 200mhz clock, when using Clocking Wizard IP?

DueProLogic by EarthPeopleTechnology: Help making it work?

Started by AwesomeCronk 2 years ago5 replieslatest reply 3 months ago121 views
I was given a DueProLogic(DPL) board last year as a birthday gift. I never could get it to work. After having built my desktop and having installed Quartus and the...

Vivado Tcl

Started by Kocsonya 9 months ago3 replieslatest reply 9 months ago107 views
I'd like to use Vivado in non-project mode, using makefiles and Tcl scripts. However, my chip is a Zynq-7000 SoC where Vivado needs to generate a module representing...

set multicycle path contradiction on hold value

Started by kaz 12 months ago129 views
Trying to solve the following contradiction about "set_multicycle_path"case 1: "Vivado using constraints" pdf states that for most cases of timing relaxing multicycle...

FPGA speed and timing closure metrics

Started by kaz 12 months ago2 replieslatest reply 12 months ago66 views
We have plenty data sheets, documents, forum replies and videos on various fpgas and designs. However what is missing in all cases is some idea how fast can one...

Aldec Active-HDL vs Modelsim PE state of play.

Started by glenenglish 1 year ago2 replieslatest reply 12 months ago75 views
What's the state of play here  in 2021 ? I have had a Modelsim PE seat in maintenance for 16 years. Modelsim has not changed, improved any done anything in that...

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