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What would be difference between clock latency and propagation delay?

Started by tip_can19 2 years ago4 replieslatest reply 2 years ago333 views
I believe the clock latency is the total time it takes from the clock source to an end point. Whereas, the propagation delay would simply be the delay between...

Activating CH7301 on SP605 board #xilinx #vhdl

Started by ajellis 3 years ago2 replieslatest reply 3 years ago194 views
HelloI am working on a project using the SP605 for a video application. Currently I'm trying to output a picture via the DVI output which is driven by a CH7301...

remains a black box sine it has not binding entity

Started by ajellis 3 years ago7 replieslatest reply 3 years ago1138 views
HI I'm working on a design where I have implemented an I2C module which I'm trying to use as a component in another piece of VHDL. The problem I've got is that...

A Law compression for FPGA

Started by kaz 3 years ago7 replieslatest reply 3 years ago133 views
Hi all,Referring to this doc on A law compression (table 1):http://www.young-engineering.com/docs/YoungEnginee...The table is meant for 13 bits signed to 8 bits...

Lattice: Utilization and Clock Report

Started by cubosubtil 3 years ago3 replieslatest reply 3 years ago53 views
Hello,I have only one clock in my design and the number of clock load in my clock report(.par) does not correspond to the number of the registers in the map report(.mrp),...

simple line drive generator doesn't work properly

Started by ombz 3 years ago3 replieslatest reply 3 years ago35 views
Hi guysI don't have any real-world experience with synthesizable VHDL and FPGA's but I've been really curious about it for a long time. So I've found an old experimenter's...

Synchronizing clock cycles of FPGA in Mojo V3 with the clock cycle of a signal generator

Started by embeddedelectronics 3 years ago4 replieslatest reply 3 years ago180 views
Hi, So I want to synchronize the clock cycle of an FPGA in mojo V3 development board, whose default clock cycle is 50 MHz with a function generator. Currently,...

BRAM based FIFO

Started by maha_66 3 years ago3 replieslatest reply 3 years ago1259 views
Hello! I am currently working on a matrix multiplication project. After performing the multiplication of the matrices, I am trying to build a module that can write...

VHDL Matrix Multiplication using UART and BRAM

Started by maha_66 3 years ago2 replieslatest reply 3 years ago310 views
My project involves performing matrix multiplication in vhdl. The two input matrices (8 bits each) are sent using a terminal and received via UART Rx. The FPGA...

Implementing octave algorithm in FPGA using c++

Started by Abhinav90 3 years ago11 replieslatest reply 3 years ago792 views
I am currently working on writing a scrambler and DeScrambler code for Orthogonal Frequency Division Multiplexing(OFDM). I am planning to write an algorithm for...

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