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Hi everyone,As part of a large FPGA/DSP project, I built a c extension library for python that mimicks the vhdl standard library fixed point functionality (https://github.com/smlgit/fpbinary)....
hi all !I am doing a BER (BIT ERROR RATE) in vhdl and I have to put 2 registers
clear on read which counts the number of words in error and the number
of bits...
Spammers are getting more sophisticated
Started by 7 years ago●4 replies●latest reply 7 years ago●572 viewsJust a quick post to inform you of a scheme used by spammers lately on the Related sites.Here's the scheme:They create an account on one of the Related sites and...
Hi All,This thought occurred to me regarding multicycle path.Assume I set multicycle of 2. Then this implies that data delay from launch edge(0) will respect the...
fpga spartan 6 io ports are no longer working
Started by 7 years ago●2 replies●latest reply 7 years ago●132 viewsHELLO there,i have spartan 6 of the familyxlc9 but i am facing a severe problem with it . first i can burn successfully with jtag on it .its power is okay but...
Todo List: Improvements to the Related Sites
Started by 7 years ago●7 replies●latest reply 7 years ago●412 viewsHere are a few improvements that I want to implement over the course of the next few weeks to the Related sites platform. Please share your thoughts, ideas and...
Altera Cyclone IV - ROM: 1-Port Problem
Started by 8 years ago●22 replies●latest reply 7 years ago●746 viewsHi,
I have created a MIF file containing 100 x 16bit values. The values point to a colour palette which contains the RGB values for 10 colours.
In Quartus Prime...
Started by Hey Guys I have been working on a key creator module for an encryption algorithm. Which uses a simple state machine to count to ten rounds of encryption. The IF...
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