Started by Misiakoulis_dev 5 years ago66 views
Hi all, I have a PYNQ-Z1 FPGA and I want to make encryption on drone communication data. At this point I want to convert a standalone application (bare metal)...

Use of DAC in ZCU111 Dev Board

Started by nicolas05 5 years ago5 replieslatest reply 5 years ago386 views
Hello Forum! ,I am a beginner with FPGA's. I want to implement an analog square wave generator using a ZCU111 Dev Board, but experiences with other boards can...

Some doubt about reset bridge

Started by nori 5 years ago1 replylatest reply 5 years ago210 views
Hi Forum,I am referring to this circuit:As you know it is well known circuit for pre-synchronizing reset (reset bridge).Looking into small details I imagine violation...

I am new to FPGA, I need guidance to understand difference between UCF andXDC

Started by mekjayk 5 years ago2 replieslatest reply 5 years ago707 views
Hello everyone,I have kintex-7 based kit https://www.avnet.com/shop/us/products/xilinx/ek-k... . I started learning about FPGA using udemy courses. where pin placement...

Reusing registers in VHDL FSM code

Started by darian16 5 years ago5 replieslatest reply 5 years ago183 views
Hello, I need to write a Finite State Machine (FSM) in VHDL code and  want to have several computations being processed at the same time (a standard pipeline)....

Tips for using Xilinx Ultra RAMs

Started by weetabixharry 5 years ago2 replieslatest reply 5 years ago2385 views
What are the main considerations that I should be aware of if I want to use Ultra RAMs in my design?I am familiar with the Block RAMs used in 5-, 6- and 7-series...

recovery/removal violations, does it always matter?

Started by kaz 5 years ago9 replieslatest reply 5 years ago1550 views
Hi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...

FPGA output pulsating in real time

Started by abdul_samad 5 years ago1 replylatest reply 5 years ago47 views
Hi,I am working on a digital down conversion module for a project of mine. The module down converts a  signal at IF 455 KHz received through an ADC, multiplies...

Fixed Point Library for Python

Started by smlgit 5 years ago7 replieslatest reply 5 years ago2072 views
Hi everyone,As part of a large FPGA/DSP project, I built a c extension library for python that mimicks the vhdl standard library fixed point functionality (https://github.com/smlgit/fpbinary)....

register clear on read

Started by kamalovich 5 years ago4 replieslatest reply 5 years ago2257 views
hi all !I am doing a BER (BIT ERROR RATE) in vhdl and I have to put 2 registers clear on read which counts the number of words in error and the number of bits...

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