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I have a pretty simple verilog project, in Lattice Diamond 3.11.My top module instantiates an OSCH (Lattice IP library) oscillator at 133 mhz, and a 'ws2812b' module...
Hi all, I have a PYNQ-Z1 FPGA and I want to make encryption on drone communication data. At this point I want to convert a standalone application (bare metal)...
Hello Forum! ,I am a beginner with FPGA's. I want to implement an analog square wave generator using a ZCU111 Dev Board, but experiences with other boards can...
Hi Forum,I am referring to this circuit:As you know it is well known circuit for pre-synchronizing reset (reset bridge).Looking into small details I imagine violation...
I am new to FPGA, I need guidance to understand difference between UCF andXDC

Hello everyone,I have kintex-7 based kit https://www.avnet.com/shop/us/products/xilinx/ek-k... . I started learning about FPGA using udemy courses. where pin placement...
Reusing registers in VHDL FSM code

Hello,
I need to write a Finite State Machine (FSM) in VHDL code and want to have several computations being processed at the same time (a standard pipeline)....
Tips for using Xilinx Ultra RAMs

What are the main considerations that I should be aware of if I want to use Ultra RAMs in my design?I am familiar with the Block RAMs used in 5-, 6- and 7-series...
recovery/removal violations, does it always matter?

Hi All,A common problem in large designs is violation on async reset. I am aware that in most cases it doesn't matter for example If I know my user logic design...
Hi,I am working on a digital down conversion module for a project of mine. The module down converts a signal at IF 455 KHz received through an ADC, multiplies...
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