Recommended references for writing a DSP IP core using Verilog.

Started by StefanOrosco 2 years ago2 replieslatest reply 2 years ago320 views
Hey all,**I am new to this forum so if this is not the correct format or information location then please let me know**I am working with an RF daughter card from...

Suggest a FPGA project

Started by sjohn 2 years ago4 replieslatest reply 2 years ago107 views
Can some one recommend a good FPGA project based on following criterion? I have done some FPGA development for fun and looking for something more serious. Criterion:1....

Learning FPGA

Started by stephaneb 2 years ago18 replieslatest reply 2 years ago2428 views
A few months ago, this community tackled the first FPGA FAQ titled When (and why) is it a good idea to use an FPGA in your embedded system design?.  Your contributions...

Pink noise generator on FPGA

Started by keffe 2 years ago3 replieslatest reply 2 years ago387 views
Hello! I want to implement a pink noise generator for audio frequencies on an FPGA, using VHDL.However, i found that not much information on this, is to find. I...

getting started with high speed parallel to serial to parallel

Started by crazy_logic 2 years ago2 replieslatest reply 2 years ago46 views
Hi all, Would anyone have advice/guidance for myself in how to create a board taking 4 serial streams (think HDMI/DVI) and serialise them to send over one link...

replacement for XILINX XC3020A-7PC84C

Started by hamed_vrz 2 years ago3 replieslatest reply 2 years ago75 views
Hi Guys,I'm looking for an similar FPGA with XILINX XC3020A-7PC84C to replace with it.i want to do this replacement with minimum changes in circuit design.I checked...

Virtual (cycle accurate) CPU simulations

Started by strubi 2 years ago3 replieslatest reply 2 years ago145 views
Hi all, I've been hacking away on a CPU builder in the past years that allows to build a microcontroller kinda from scratch with some standard peripherals in...

MachXO2 I2C configuration. EFB I2C block synthesis error.

Started by atom1477 2 years ago2 replieslatest reply 2 years ago226 views
Hello.I creating project with LCMXO2-1200HC device in QFN32 package, so i have very limited number of IO pins and I want to configuring FPGA by I2C instead of JTAG.I...

How to understand -edge option if first edge of generated clock is falling edge?

Started by tip_can19 2 years ago1 replylatest reply 2 years ago60 views
I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like below:I...

What would be difference between clock latency and propagation delay?

Started by tip_can19 2 years ago4 replieslatest reply 2 years ago305 views
I believe the clock latency is the total time it takes from the clock source to an end point. Whereas, the propagation delay would simply be the delay between...

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