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Intel Quartus Prime Lite Edition asks for license even though their website says that license isn't required
Started by 7 years ago●4 replies●latest reply 7 years ago●3062 viewsI am trying to bring up the DE10 Nano kit that has Cyclone V FPGA using the open source Cascade compiler https://github.com/vmware/cascade from VMware. It uses Quartus...
Hello everyone.Currently, Im designing a processing element.This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.I have problem...
VHDL : function not recognizing a type defined in package
Started by 7 years ago●1 reply●latest reply 7 years ago●456 viewsHi,I am trying to write a function that reads from csv file and formats data to fixed point so it can be used to initialize ROM contents.The function is contained...
HELP NEEDED - FPGA related Christmas present suggestions
Started by 7 years ago●1 reply●latest reply 7 years ago●108 viewsHi, I know nothing about FPGA, integrated circuits, electronics, et cetera. I do know that it's a field my father is interested in. A little background, he's worked...
DueProLogic by EarthPeopleTechnology: Help making it work?
Started by 7 years ago●5 replies●latest reply 7 years ago●298 viewsI was given a DueProLogic(DPL) board last year as a birthday gift. I never could get it to work. After having built my desktop and having installed Quartus and the...
Recently I came into the possession of a ML310 (Virtex-II Pro) board made by Xilinx. IT is an old board and unfortunately, except for a few User Guides nothing can...
Due to lack of support from lattice - and also mi lack of experiece with Lattice: I come from the xlinx world - I am here to get help about integrating this IP on...
Timing paths from wires to registers
Started by 7 years ago●3 replies●latest reply 7 years ago●134 viewsHi All,I 've come across this case (please see figure below) .I have a synchronous system but four constants (A,B,C,D) are implemented on wires and any one of them...
How to use non-dedicated IO pins as clock source to FPGA PLL or Clock MUX?I try to use "PROHIBIT PRIMARY" preference, as described in:TN1263 ECP5 and ECP5-5G sysCLOCK...
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