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Completely OT: Your Favorite 'Relatively Unknown' Music
Started by 6 years ago●13 replies●latest reply 6 years ago●582 viewsSo far, we've been very good at staying on-topic in the *Related sites forums. Today, let me break the trend and start a completely off-topic (#OT) thread that...
Aurora 8B10B for Virtex-4 FX FPGA Generation Failed Using ISE 14.7
Started by 6 years ago●2 replies●latest reply 6 years ago●106 viewsI am trying to generate the Aurora 8B10B core for Virtex-4 FPGA using ISE 14.7 in Windows 7 (64 bit) OS based on the procedure presented in LogiCore IP guide....
Best FPGA for Harvard Architecture
Started by 6 years ago●3 replies●latest reply 6 years ago●130 views(a) I am prototyping a new CPU (Harvard Architecture) with separate 1MB program memory and 1MB data memory. Which Xilinx FPGA board would be the best choice...
transfert data from host pc to target fpga using DMA
Started by 6 years ago●6 replies●latest reply 6 years ago●241 viewsI have 2 image files imported by ENVI tool (png or raster file), and they are stored in my hard disk, I want to transfer this data from host PC to target FPGA using...
I am currently at Embedded World in Germany (tomorrow is the last day) and with more than 1000 vendors, most relevant players in the industry are here this week.I...
A current active contract role for an FPGA engineer is around but sounds very strange in that it tries to explain the FPGA more than the required skills for the...
FPGA perspective of pins versus PCB perspective
Started by 6 years ago●2 replies●latest reply 6 years ago●85 viewsHi All,I am looking for any hints on FPGA pin constraints and their PCB perspective.Are there any established rules for both designers (FPGA & PCB) to work...
Ideas for simple bitrate regulation
Started by 6 years ago●5 replies●latest reply 6 years ago●202 viewsHello everyone,I would like to implement a bitrate regulation on an fpga board.Clock + data are incoming at bitrate with a +/- percentage. Then after a channel coder...
If FPGAs didn't work we won't be here?
Started by 6 years ago●2 replies●latest reply 6 years ago●121 viewsBeing over-careful is good practice especially for presentation to the management but factual issues should not be distorted for that sake.What I mean if an FPGA...
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