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Hello everyone, I find a xilinx zynq single board computer Z-turn board, the price is attractive and I would like to order one for my evaluation. But I find it has...
Hi
I planning to do my research in Deep Learning in FPGA.
Can you suggest any specific research topics within this fiels ?
What is the scope of the field ?
Hi there,I am engineering a makefile based build system for FPGA based projects.I was considering making a blog entry with my challenges, solutions, and thoughts. Would...
Started by Hi, I don't know if I am allowed to ask this question, because it is complicated but I tried searching couldn't find anything that helped, so my question is stupid...
I am working on a project using the cyclone V from Altera. The FPGA has 3.3v GPIO pins and I would like to know what I could use to mimic a GPIO pins output. I am...
Overloading assignment operator '<=' in vhdl
Started by 7 years ago●1 reply●latest reply 7 years ago●441 views...
I am designing the FIR filter for up conversion in FPGA. Input to the FIR filter is 16 bits wide (-32768 to 32767) with the maximum co-eff value of 32767. This produces...
FPGA and VHDL Language for beginner
Started by 7 years ago●3 replies●latest reply 7 years ago●146 viewsHi, my name is IMA and I am now studying about
the FPGA VHDL language to generate the gate signal for my
converter circuit. I have basic C++ programming...
Synplify Pro for Lattice not working
Started by 7 years ago●4 replies●latest reply 7 years ago●1039 viewsI put in a support ticket with Lattice. Nothing they suggested I try worked. Except installing on another Windows box. When I did not get the error on the other...
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