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Started by If I implemented the new email notification system well, this new thread should trigger an email notification to all members who have been approved to participate...
Guidelines for porting ASIC RTL to FPGA
Started by 7 years ago●3 replies●latest reply 7 years ago●1000 viewsI wonder what are the guidelines for porting ASIC RTL to FPGA for emulation.1. Memory blocks need be adjusted for FPGA device specific features.2. DSP Elements...
DDC in FPGA with high speed ADC
Started by 7 years ago●14 replies●latest reply 7 years ago●1953 viewsHi allI'm going to work with high speed ADC in my upcoming project. I'm having 4 ADC channels with 3.2GHz sampling rate interfaced with FPGA. I'm getting 40 samples...
Maybe you've seen my latest blog post? Producing these videos has been very fun and I plan on doing many more in the future. If you only have a couple of minutes,...
what is line 19 of http://paste2.org/MGVm0751 trying to do ? it seems to me that it is transformed into 2-complement, but I do not think that is the purpose. Anyone...
Synchronizing Multiple FPGA Prototype Boards
Started by 7 years ago●8 replies●latest reply 7 years ago●1127 viewsMy project requires large numbers of IO lines.I love the dedicated ATmega32U4 processor for serial comms on the Mojo, it runs lickety split with it's cut down optimised...
Dear all,
This is probably an always re-occurring topic within electronics forums and one that probably leads to plenty of subjective inputs and hence: discussion....
sampling 800mbps data in virtex 5QV
Started by 7 years ago●9 replies●latest reply 7 years ago●100 viewsWe are trying for a space radar application. For that from ADC need to receive data at around 760MHz.Is it possible to achieve using rocketio ?
Packaging custom IP (master) in XPS
Started by 7 years ago●1 reply●latest reply 7 years ago●102 viewsHi, I need to package a customized master IP with a set of hdl files, using XPS tool. As I am using Spartan 6 FPGA, I cannot use Vivado. Can anyone guide in doing...
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