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SystemFaXflow_and_Issues.pdfWe have been through some issues with integration of FAX Relay into TTMS320C55XX. The Object code for the FAX relay was from a TI Third...
Use Microblaze performance monitoring engine
Started by 8 years ago●6 replies●latest reply 8 years ago●351 viewsHi,I would like to use the #MicroBlaze performance monitoring engine to
collect some information on my application code running on the processor
itself. I would...
Generating a Block Design in Vivado from existing Verilog & IP files
Started by 8 years ago●2 replies●latest reply 8 years ago●6619 viewsI have a #Vivado project that I pieced together from #Verilog and IP files from a Github repository. I believe the project was originally created in ISE as there...
Max IO speed for capturing Source Sync Data into an FPGA
Started by 8 years ago●3 replies●latest reply 8 years ago●132 viewsHi - I'm looking into capturing data into an FPGA from a device that can supply either 80 or 160 bit wide data with a source sync clock. The data rate can be...
Why vendors insist on creating block-diagram editors
Started by 8 years ago●10 replies●latest reply 8 years ago●1483 viewsBoth XIlinx and Altera waste copious amount of time and resources creating tools to "help" FPGA system designers. The issue, in my opinion, is that these tools...
Is it just me or are some FPGA people very protective?
Started by 8 years ago●6 replies●latest reply 8 years ago●192 viewsI'm just a newbie when it comes to FPGA. I do have a few successful projects under my belt, but I'm not so brave to think that's enough to call myself an FPGA engineer.However,...
Code review. Newbie's first verilog module!
Started by 8 years ago●4 replies●latest reply 8 years ago●331 viewsHi This is one of the first verilog modules I wrote. It reads a 1-Wire iButton / Dallas keyfob code.The theory of operation is that approximately every two seconds...
Welcome to the New Forum Interface!
Started by 8 years ago●15 replies●latest reply 8 years ago●709 viewsAfter months of hard word, I am very excited to introduce to you the new forum interface. It will be the foundation of the related sites for the next several...
Best method for a large dot vector
Started by 8 years ago●13 replies●latest reply 8 years ago●123 viewsI am trying to compute a 274 sample dot vector in an FPGA (in #Verilog). I have the clock cycles to compute it over many clocks, but I am having trouble meeting...
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