Mounting a game On FPGA

Started by obenyaala 2 years ago6 replieslatest reply 2 years ago176 views
Hi, I don't know if I am allowed to ask this question, because it is complicated but I tried searching couldn't find anything that helped, so my question is stupid...

Effective schematic for GPIO pin

Started by l8rPIC 2 years ago1 replylatest reply 2 years ago120 views
I am working on a project using the cyclone V from Altera. The FPGA has 3.3v GPIO pins and I would like to know what I could use to mimic a GPIO pins output. I am...

Overloading assignment operator '<=' in vhdl

Started by LabPe43 2 years ago1 replylatest reply 2 years ago191 views

DSP Filter Verification in FPGA

Started by srid 2 years ago30 replieslatest reply 2 years ago328 views
I am designing the FIR filter for up conversion in FPGA. Input to the FIR filter is 16 bits wide (-32768 to 32767) with the maximum co-eff value of 32767. This produces...

Programmable SoC and SoC FPGA

Started by jbmore 2 years ago5 replieslatest reply 2 years ago454 views
Hello, What's the difference between Programmable SoC and SoC FPGA ?  Thank you

FPGA and VHDL Language for beginner

Started by hey_gluppy 2 years ago3 replieslatest reply 2 years ago93 views
Hi, my name is IMA and I am now studying about the FPGA VHDL language to generate the gate signal for my converter circuit. I have basic C++ programming...

Synplify Pro for Lattice not working

Started by CraigMeyers 2 years ago4 replieslatest reply 2 years ago221 views
I put in a support ticket with Lattice. Nothing they suggested I try worked. Except installing on another Windows box. When I did not get the error on the other...

New Email Notifications System

Started by stephaneb 3 years ago5 replieslatest reply 2 years ago194 views
If I implemented the new email notification system well, this new thread should trigger an email notification to all members who have been approved to participate...

Guidelines for porting ASIC RTL to FPGA

Started by LabPe43 2 years ago3 replieslatest reply 2 years ago412 views
I wonder what are the guidelines for porting ASIC RTL to FPGA for emulation.1. Memory blocks need be adjusted for FPGA device specific features.2. DSP Elements...

DDC in FPGA with high speed ADC

Started by LoganathanN 2 years ago14 replieslatest reply 2 years ago798 views
Hi allI'm going to work with high speed ADC in my upcoming project. I'm having 4 ADC channels with 3.2GHz sampling rate interfaced with FPGA. I'm getting 40 samples...

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