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Started by Hi, I don't know if I am allowed to ask this question, because it is complicated but I tried searching couldn't find anything that helped, so my question is stupid...
I am working on a project using the cyclone V from Altera. The FPGA has 3.3v GPIO pins and I would like to know what I could use to mimic a GPIO pins output. I am...
Overloading assignment operator '<=' in vhdl
Started by 2 years ago●1 reply●latest reply 2 years ago●191 views...
I am designing the FIR filter for up conversion in FPGA. Input to the FIR filter is 16 bits wide (-32768 to 32767) with the maximum co-eff value of 32767. This produces...
FPGA and VHDL Language for beginner
Started by 2 years ago●3 replies●latest reply 2 years ago●93 viewsHi, my name is IMA and I am now studying about
the FPGA VHDL language to generate the gate signal for my
converter circuit. I have basic C++ programming...
Synplify Pro for Lattice not working
Started by 2 years ago●4 replies●latest reply 2 years ago●221 viewsI put in a support ticket with Lattice. Nothing they suggested I try worked. Except installing on another Windows box. When I did not get the error on the other...
Started by If I implemented the new email notification system well, this new thread should trigger an email notification to all members who have been approved to participate...
Guidelines for porting ASIC RTL to FPGA
Started by 2 years ago●3 replies●latest reply 2 years ago●412 viewsI wonder what are the guidelines for porting ASIC RTL to FPGA for emulation.1. Memory blocks need be adjusted for FPGA device specific features.2. DSP Elements...
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