Forums
Hi,I can't seem to find a QSPI slave IP core. Any pointers? My application needs to interface with a QSPI master interface on a processor.Thanks
Use example of Intel University program in Intel Quartus - problem with Board support package?
Started by 4 years ago●47 views
I want to use a example from the Intel FPGA Monitor Program 18.1 and use it in Quartus 18.1.
It is the video example, which creates a blue box on the HDMI...
Final Push and Could use your Help
Started by 4 years ago●234 viewsHello,by now, I suspect that most of you are already signed-up for the upcoming Embedded Online Conference that I am currently organizing with Jacob Beningo (@beningjw).I...
UDP or TCP/IP FPGA solution for max streaming rate of 640 Mbps
Started by 4 years ago●6 replies●latest reply 4 years ago●346 viewsHi,I am an FPGA engineer in charge of developing a test application that must offload a continuous test data stream between host PC and a test hardware. I do not...
New Embedded Online Conference website, need your help testing it.
Started by 4 years ago●15 replies●latest reply 4 years ago●280 viewsTogether with my friend Jacob Beningo, we have been working hard lately on putting together a platform to hold online conferences:https://www.embeddedonlineconference.comBefore...
Hello,I implemented running sum filter In FPGA. Input width(IW) is 8 and the log(based two) of the maximum number of averages(LGMEM) is 14. The output/accumulator...
Edit #1 01/19 10:12am: well, false start with the new host. Their migration team was supposed to help me through the process this morning but I am not hearing...
It looks like the migration went well. I found a couple of errors but solved them quickly. I will continue to do some testing to make sure that everything is...
Intel Quartus Prime Lite Edition asks for license even though their website says that license isn't required
Started by 4 years ago●4 replies●latest reply 4 years ago●2089 viewsI am trying to bring up the DE10 Nano kit that has Cyclone V FPGA using the open source Cascade compiler https://github.com/vmware/cascade from VMware. It uses Quartus...
timing analysis query
Started by 4 years ago●39 viewsHello everyone.Currently, Im designing a processing element.This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484.I have problem...
Please login (on the right) if you already have an account on this platform.
Otherwise, please use this form to register (free) an join one of the largest online community for Electrical/Embedded/DSP/FPGA/ML engineers: