Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
MyHDL FPGA Tutorial I (LED Strobe)
Skip Verilog and try MyHDL, a Python-based HDL, to build and simulate an FPGA LED strobe in this hands-on tutorial. Christopher Felton walks through a parameterized LED shifter, py.test driven verification, and automated conversion to Verilog and bitstreams for several development boards. The post includes scripts to generate pin constraints and run vendor tools so you can build and program boards from one language.
FPGA or DSP Processor - Parameters to Make the Right Choice
Muhammad Yasir breaks down the practical tradeoffs between FPGAs and DSP processors for real-world signal-processing systems. He offers concrete rules of thumb on sampling-rate and data-rate limits, MMAC performance bands, and when conditional logic or floating-point favors a DSP. The post also covers power, form factor, maintainability, and development-time tradeoffs to help architects pick the right platform.
Introduction to FPGA Technology
Muhammad Yasir lays out a concise primer on FPGA fundamentals, covering internal architecture, vendors, and practical selection criteria. He explains how logic cells, LUTs, flip-flops, carry chains, block RAM, and I/O blocks combine to determine capacity and performance. This friendly overview shows why FPGAs beat ASICs for low-volume or rapidly changing designs, and how to match device resources to your application needs.
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
MyHDL ... MyPWM
Christopher Felton presents a compact MyHDL PWM engine designed to be configured at design time and targeted for FPGA synthesis. The module derives PWM bit width from the system clock frequency and desired pwm_frequency, truncates inputs when necessary, and prints parameter summaries for different clock/pwm combinations. The post includes the full MyHDL source and a simulation waveform showing the input signal and the modulated output, making it easy to reproduce.
binary hello world
Christopher Felton walks through two minimalist "binary hello world" examples that make FPGA basics approachable using Python and MyHDL. Attendees wire a button to an LED, add a flip-flop to introduce registers, then implement debouncing and blink-rate control, all compiled with simple Python scripts that drive the FPGA tool flow. Complete source is available on Bitbucket for hands-on experimentation.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
Choosing an Implementation Approach
I outline why I chose a CPU-like Graph Cut Processing Unit for FPGA-based graph-cut work, contrasting whole-problem and streaming approaches from the literature. The plan maps push-relabel style augmenting-path iterations to a simple GCPU state machine and pseudocode, prioritizing staged, testable development now and leaving highly parallel streaming scaling for later.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
Polynomial Math
This post walks through squaring and inversion in a tiny finite field to make ECC math tangible. Using GF(2^5) with primitive polynomial beta^5 + beta^2 + 1 it shows why squaring cancels cross terms so you only need half the lookup table, and how Fermat exponentiation computes inverses via repeated squarings and multiplies. It also demonstrates the Extended Euclid polynomial inverse and compares FPGA and CPU tradeoffs.
Designing a FPGA Micro Pt2 - Clock and Counter build and test.
Paul J Clarke continues building his PIC12F509-style soft core by implementing the clock and program counter. He walks through a simple clock_gen.vhd that rotates a four-bit shift register to produce Q1 to Q4 phases, wires it into monpjc_pic_core.vhd for a XuLA target, and adds a 12-bit integer pc_counter that increments on Q1. The post shows simulation testbench results and previews stack and memory work next.
Elliptic Curve Digital Signatures
Elliptic curve digital signatures deliver compact, strong message authentication by combining a hash of the message with elliptic curve point math. This post walks through the standard sign and verify equations, showing why recomputing a point R' yields the same x coordinate only when the hash matches. It also explains the Nyberg-Rueppel alternative that removes modular inversion and an FPGA-friendly trick of transmitting point D to avoid integer modular arithmetic.
MyHDL ... MyPWM
Christopher Felton presents a compact MyHDL PWM engine designed to be configured at design time and targeted for FPGA synthesis. The module derives PWM bit width from the system clock frequency and desired pwm_frequency, truncates inputs when necessary, and prints parameter summaries for different clock/pwm combinations. The post includes the full MyHDL source and a simulation waveform showing the input signal and the modulated output, making it easy to reproduce.
Choosing an Implementation Approach
I outline why I chose a CPU-like Graph Cut Processing Unit for FPGA-based graph-cut work, contrasting whole-problem and streaming approaches from the literature. The plan maps push-relabel style augmenting-path iterations to a simple GCPU state machine and pseudocode, prioritizing staged, testable development now and leaving highly parallel streaming scaling for later.
Grandiose Delusions
Christopher Felton admits his big plans for an open-source MyHDL IP ecosystem never quite finished, and explains why. He reflects on scope creep, hobby-time distractions, and excessive tool-building that slowed progress. The post is a candid look at what it takes to produce production-quality FPGA IP: documentation, regression tests, and hardware validation.
My VHDL <= monpjc; Journey
Paul J Clarke (monpjc) traces his VHDL journey from Altera SDRAM interfaces to hobby MAX7000 projects and how affordable dev kits rekindled his FPGA hobby. He explains why he prefers VHDL, why Xilinx ISE won him over, and urges engineers to learn by doing with simple projects. The post offers practical kit recommendations and teases a follow-up series on building a CPU on an FPGA.
