BGA and QFP at Home 1 - A Practical Guide.
It's a myth that BGAs and fine-pitch QFPs can't be soldered at home. Victor Yurkovsky lays out a practical, no-frills approach for hobbyists to design and assemble FPGA boards using 2-layer PCBs, breakout modules, and low-cost reflow methods like toaster ovens or hotplates. The article focuses on manufacturable PCB choices, netlist-driven workflows, and power/decoupling tactics that make high-density parts approachable for amateurs.
Windows XP and Win32 - the Platform of the Future!
Victor Yurkovsky makes the contrarian case that an offline Windows XP VM running Win32 is the most practical platform for modern FPGA development. He explains how Xilinx ISE and related tools often behave far better under XP than on modern Linux distributions, and how VirtualBox fixes USB and GUI headaches. If you maintain FPGA toolchains or write compact C/C++ utilities, this retro setup can save time and frustration.
binary hello world
Christopher Felton walks through two minimalist "binary hello world" examples that make FPGA basics approachable using Python and MyHDL. Attendees wire a button to an LED, add a flip-flop to introduce registers, then implement debouncing and blink-rate control, all compiled with simple Python scripts that drive the FPGA tool flow. Complete source is available on Bitbucket for hands-on experimentation.
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
MyHDL ... MyPWM
Christopher Felton presents a compact MyHDL PWM engine designed to be configured at design time and targeted for FPGA synthesis. The module derives PWM bit width from the system clock frequency and desired pwm_frequency, truncates inputs when necessary, and prints parameter summaries for different clock/pwm combinations. The post includes the full MyHDL source and a simulation waveform showing the input signal and the modulated output, making it easy to reproduce.
Yet another PWM
The provided record for Anton Babushkin’s post “Yet another PWM” contains no article body, so the actual technical content is not available for review. The title and site context indicate the post concerns pulse-width modulation (PWM), but specific implementation details, language, or examples cannot be confirmed from the supplied input. This metadata therefore documents the absence of content, recommends steps to recover the original post, and flags that any downstream use (tagging, excerpts, or code extraction) must wait until the full text is retrieved from FPGARelated’s archive or the author’s copy to avoid misrepresentation.
MyHDL Resources and Projects
Christopher Felton has pulled together a compact, practical guide to learning and using MyHDL, with the essential manual, Jan Decaluwe's deep dives, presentations, example projects, and active Git/Bitbucket repos. Whether you want a tutorial path, reference reads, or hands-on FPGA projects from simple LEDs to SDR and DSP cores, this curated list points you to vetted resources and real designs to study and reuse.
How to start in FPGA development? - Some tips
Starting from zero, this practical primer walks new FPGA users through the early decisions and habits that make projects work. Nuria Orduna covers how to pick a device, sketch a clear dataflow, prototype in MATLAB or C, organize VHDL entities versus functions, and use ModelSim .do files and testbenches to debug before programming the board. Read it for concise, hands-on starting points.
MyHDL FPGA Tutorial II (Audio Echo)
Christopher Felton demonstrates how to build an FPGA audio echo using MyHDL by storing delayed samples in BRAM and mixing them back with incoming audio. The project shows parameterizable sample rate, sample width, buffer depth, and conversion from MyHDL to Verilog, with a strong emphasis on test-driven verification and simulation-based resource reports. Read on to see how delay, scaling, and BRAM usage affect real-time audio.
One Clock Cycle Polynomial Math
Error correction codes and cryptographic computations are most easily performed working with GF(2^n)
Learning VHDL - Basics
Enrico Garante walks through a compact, hands-on introduction to VHDL and Xilinx ISE, using the affordable Basys2 board. The tutorial explains entity versus architecture, the IEEE.STD_LOGIC_1164 types, and how to write a process with a sensitivity list to implement a simple AND gate. A short ISim video demo shows project creation and simulation so you can verify designs before programming the board.
Polynomial Math
This post walks through squaring and inversion in a tiny finite field to make ECC math tangible. Using GF(2^5) with primitive polynomial beta^5 + beta^2 + 1 it shows why squaring cancels cross terms so you only need half the lookup table, and how Fermat exponentiation computes inverses via repeated squarings and multiplies. It also demonstrates the Extended Euclid polynomial inverse and compares FPGA and CPU tradeoffs.
Introduction to FPGA Technology
Muhammad Yasir lays out a concise primer on FPGA fundamentals, covering internal architecture, vendors, and practical selection criteria. He explains how logic cells, LUTs, flip-flops, carry chains, block RAM, and I/O blocks combine to determine capacity and performance. This friendly overview shows why FPGAs beat ASICs for low-volume or rapidly changing designs, and how to match device resources to your application needs.
Elliptic Curve Key Exchange
Elliptic Curve key exchange gives a fresh secret for every session so past messages stay safe even if one key is discovered. This post walks through an ElGamal-style ephemeral exchange and the MQV protocol, showing how MQV mixes static and random keys to provide mutual authentication and forward secrecy. It also explains how MQV can be implemented using only curve operations to save FPGA area and why erasing ephemeral values matters.
Elliptic Curve Digital Signatures
Elliptic curve digital signatures deliver compact, strong message authentication by combining a hash of the message with elliptic curve point math. This post walks through the standard sign and verify equations, showing why recomputing a point R' yields the same x coordinate only when the hash matches. It also explains the Nyberg-Rueppel alternative that removes modular inversion and an FPGA-friendly trick of transmitting point D to avoid integer modular arithmetic.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
MyHDL Resources and Projects
Christopher Felton has pulled together a compact, practical guide to learning and using MyHDL, with the essential manual, Jan Decaluwe's deep dives, presentations, example projects, and active Git/Bitbucket repos. Whether you want a tutorial path, reference reads, or hands-on FPGA projects from simple LEDs to SDR and DSP cores, this curated list points you to vetted resources and real designs to study and reuse.
How to start in FPGA development? - Some tips
Starting from zero, this practical primer walks new FPGA users through the early decisions and habits that make projects work. Nuria Orduna covers how to pick a device, sketch a clear dataflow, prototype in MATLAB or C, organize VHDL entities versus functions, and use ModelSim .do files and testbenches to debug before programming the board. Read it for concise, hands-on starting points.
State Machine ‘v’ Micro in a FPGA
A CPU is just a big state machine, but that doesn't mean you always need one in your FPGA. Paul compares hand-written state machines, soft-core CPUs, and standalone microcontrollers, highlighting speed, flexibility, cost, and complexity tradeoffs. Read this if you want a practical way to decide whether to add more state machines, a small soft core, or a separate MCU to your next design.
Why I would choose an FPGA development board?
FPGA boards are the smarter choice for hands-on learning and flexible hardware design. Compared with microcontroller dev boards, they let you run many hardware tasks in parallel, reuse the same HDL across different vendors, and even host soft-core microcontrollers inside the fabric. This post walks through those practical advantages and points out modern low-cost boards that make FPGAs accessible for students and engineers.
MyHDL Resources and Projects
Christopher Felton has pulled together a compact, practical guide to learning and using MyHDL, with the essential manual, Jan Decaluwe's deep dives, presentations, example projects, and active Git/Bitbucket repos. Whether you want a tutorial path, reference reads, or hands-on FPGA projects from simple LEDs to SDR and DSP cores, this curated list points you to vetted resources and real designs to study and reuse.
Windows XP and Win32 - the Platform of the Future!
Victor Yurkovsky makes the contrarian case that an offline Windows XP VM running Win32 is the most practical platform for modern FPGA development. He explains how Xilinx ISE and related tools often behave far better under XP than on modern Linux distributions, and how VirtualBox fixes USB and GUI headaches. If you maintain FPGA toolchains or write compact C/C++ utilities, this retro setup can save time and frustration.
One Clock Cycle Polynomial Math
Error correction codes and cryptographic computations are most easily performed working with GF(2^n)
binary hello world
Christopher Felton walks through two minimalist "binary hello world" examples that make FPGA basics approachable using Python and MyHDL. Attendees wire a button to an LED, add a flip-flop to introduce registers, then implement debouncing and blink-rate control, all compiled with simple Python scripts that drive the FPGA tool flow. Complete source is available on Bitbucket for hands-on experimentation.
Polynomial Inverse
One of the important steps of computing point addition over elliptic curves is a division of two polynomials.
Elliptic Curve Key Exchange
Elliptic Curve key exchange gives a fresh secret for every session so past messages stay safe even if one key is discovered. This post walks through an ElGamal-style ephemeral exchange and the MQV protocol, showing how MQV mixes static and random keys to provide mutual authentication and forward secrecy. It also explains how MQV can be implemented using only curve operations to save FPGA area and why erasing ephemeral values matters.
USB-FPGA : Introduction
Christopher Felton recounts a six-year hobby project to build an open-source USB-FPGA board and its toolchain, from PCB to gateware, firmware, and PC software. He explains why the Cypress FX2 and a Spartan3 were chosen, how the USBP framework supported multiple boards, and why the project’s open-source ambitions didn’t attract the collaboration he expected. Expect practical design and community lessons.
MyHDL Interface Example
Christopher Felton shows how MyHDL 0.9 interfaces bundle Signals into a single bus object to cut connector clutter and simplify module connections. The post walks through a pedagogical example where button presses drive a memory-mapped BareBoneBus read-modify-write that inverts LEDs, with a TDD-style testbench and notes on converting to Verilog/VHDL and loading the example on supported boards.
Designing a FPGA Micro Pt1 - Start The Clock
Paul J Clarke takes on cloning a Microchip PIC12F509 inside an FPGA, picking it for its tiny, well-documented architecture. He outlines the core pieces you'll need: 1024×12-bit ROM, 41 bytes of RAM, an ALU, status register, program counter with a two-level stack, GPIO, and the PIC's unusual four-phase internal clock. This post sets the plan and previews the next installment with the first implementation work.
