Why I would choose an FPGA development board?
Some years ago, when I went to the University, I bought some development boards based on different microcontrollers, and I remember that, although development boards were not expensive, I had to add to the price of the board, the shipping costs and the taxes, which were more than the 50% of the price of the board, but there are no option if I wanted to test that microcontroller. When I wanted to test some other feature, I had to buy a different board, for example, if I wanted to design some...
A New Related Site!
We are delighted to announce the launch of the very first new Related site in 15 years! The new site will be dedicated to the trendy and quickly growing field of Machine Learning and will be called - drum roll please - MLRelated.com.
We think MLRelated fits perfectly well within the “Related” family, with:
- the fast growth of TinyML, which is a topic of great interest to the EmbeddedRelated community
- the use of Machine/Deep Learning in Signal Processing applications, which is of...
The DSP Online Conference - Right Around the Corner!
It is Sunday night as I write this blog post with a few days to go before the virtual doors of the very first DSP Online Conference open..
It all started with a post in the DSPRelated forum about three months ago. We had just had a blast running the 2020 Embedded Online Conference and we thought it could be fun to organize a smaller event dedicated to the DSP community. So my goal with the post in the forum was to see if...
Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm
Introduction
A well known algorithm for computing square roots by iteration is provided by the Newton-Raphson Algorithm. The algorithm determines the square root using iteration until the root has been determined to some user-defined level of accuracy. The method is easily derived. First, describe a number in terms of its square root:
$$ a = y ^ {2} ,$$
where $y = \sqrt{a}$. The value of the $\sqrt{a}$ can be written as $y = y_0 + \epsilon$, where $y_0$ is the value of the square root and...
MyHDL synthesis: from browser to FPGA in five seconds
When it comes to feeding (mostly proprietary) synthesis tools, the most widely supported HDL (hardware design language) is probably plain Verilog, then comes VHDL. The reasons for that are simply based on popularity or the fact that VHDL is a little more complex to parse.
So, all super-HDLs (like Chisel, SpinalHDL, etc.) transfer to one of these V* HDLs in one way or another, then synthesis/mapping/place'n'route turns it into a wiring map for the silicon. Same went for MyHDL or its also...
Already 3000+ Attendees Registered for the Upcoming Embedded Online Conference
Chances are you already know, through the newsletter or banners on the Related sites, about the upcoming Embedded Online Conference.
Chances are you also already know that you have until the end of the month of February to register for free.
And chances are that you are one of the more than 3000 pro-active engineers who have already registered.
But If you are like me and have a tendency to do tomorrow what can be done today, maybe you haven't registered yet. You may...
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
This final article in the series will look at -ve latency DSP and how it can be used to cancel the unwanted delays in sampled-data systems due to such factors as Nyquist filtering, ADC acquisition, DSP/FPGA algorithm computation time, DAC reconstruction and circuit propagation delays.
Some applications demand zero-latency or zero unwanted latency signal processing. Negative latency DSP may sound like the stuff of science fiction or broken physics but the arrangement as...
Free Goodies from Embedded World - Full Inventory and Upcoming Draw Live-Streaming Date
Chances are that you already know that I went to Embedded World a few weeks ago and came back with a bag full of "goodies". Initially, my vision was to do a single draw for one person to win it all, but I didn't expect to come back with so much stuff and so many development kits. Based on your feedback, it seems like you guys agree that It wouldn't make sense for one person to win everything as no-one could make good use of all the boards and there would be lots of...
Free Goodies from Embedded World - What to Do Next?
I told you I would go on a hunt for free stuff at Embedded World in order to build a bundle for someone to win.
Back from Embedded World 2019 - Funny Stories and Live-Streaming Woes
When the idea of live-streaming parts of Embedded World came to me, I got so excited that I knew I had to make it happen. I perceived the opportunity as a win-win-win-win.
- win #1 - Engineers who could not make it to Embedded World would be able to sample the huge event,
- win #2 - The organisation behind EW would benefit from the extra exposure
- win #3 - Lecturers and vendors who would be live-streamed would reach a (much) larger audience
- win #4 - I would get...
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.
Fig 1. Making a Transmission Line, with the Circuit Emulator
Additional...
Already 3000+ Attendees Registered for the Upcoming Embedded Online Conference
Chances are you already know, through the newsletter or banners on the Related sites, about the upcoming Embedded Online Conference.
Chances are you also already know that you have until the end of the month of February to register for free.
And chances are that you are one of the more than 3000 pro-active engineers who have already registered.
But If you are like me and have a tendency to do tomorrow what can be done today, maybe you haven't registered yet. You may...
How FPGAs work, and why you'll buy one
Today, pretty much everyone has a CPU, a DSP and a GPU, buried somewhere in their PC, phone, car, etc. Most don't know or care that they bought any of these, but they did.
Will everyone, at some future point, also buy an FPGA? The market size of FPGAs today is about 1% of the annual global semiconductor sales (~$3B vs ~$300B). Will FPGA eventually...
VHDL tutorial - A practical example - part 3 - VHDL testbench
In part 1 of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part. In part 2, we described the VHDL logic of the CPLD for this design. In part 3, we will show the entire VHDL design and the associated tests used to prove that we have, in fact, designed what we started out to design.
First, let's pull all of the pieces of the prior design together into a...
A New Related Site!
We are delighted to announce the launch of the very first new Related site in 15 years! The new site will be dedicated to the trendy and quickly growing field of Machine Learning and will be called - drum roll please - MLRelated.com.
We think MLRelated fits perfectly well within the “Related” family, with:
- the fast growth of TinyML, which is a topic of great interest to the EmbeddedRelated community
- the use of Machine/Deep Learning in Signal Processing applications, which is of...
Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm
IntroductionA well known algorithm for computing square roots by iteration is provided by the Newton-Raphson Algorithm. The algorithm determines the square root using iteration until the root has been determined to some user-defined level of accuracy. The method is easily derived. First, describe a number in terms of its square root:
$$ a = y ^ {2} ,$$
where $y = \sqrt{a}$. The value of the $\sqrt{a}$ can be written as $y = y_0 + \epsilon$, where $y_0$ is the value of the square root and...
Why I would choose an FPGA development board?
Some years ago, when I went to the University, I bought some development boards based on different microcontrollers, and I remember that, although development boards were not expensive, I had to add to the price of the board, the shipping costs and the taxes, which were more than the 50% of the price of the board, but there are no option if I wanted to test that microcontroller. When I wanted to test some other feature, I had to buy a different board, for example, if I wanted to design some...
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
IntroductionThis article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.
To stay true to the original design, I...
Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines
IntroductionThis article will describe a synthesizable HDL-based microprogram controller (MPC), or microprogram sequencer (MPS), that can be used to provide the control of a microprogrammed state machine. Unlike the microprogrammed state machines that I described in my previous two articles, "Use Microprogramming to Save Resources and Add Functionality" and "Fit Sixteen (or more) Asynchronous Serial Receivers in the Area of a Standard UART", many microprogrammed state machines will...
Use DPLL to Lock Digital Oscillator to 1PPS Signal
IntroductionThere are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency oscillator on the leading edge of the 1PPS signal. In many cases, this will result in adequate performance. However, in situations where simple synchronization does not provide adequate performance, digital phase-lock techniques can be applied to a...
VHDL tutorial - A practical example - part 3 - VHDL testbench
In part 1 of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part. In part 2, we described the VHDL logic of the CPLD for this design. In part 3, we will show the entire VHDL design and the associated tests used to prove that we have, in fact, designed what we started out to design.
First, let's pull all of the pieces of the prior design together into a...
How FPGAs work, and why you'll buy one
Today, pretty much everyone has a CPU, a DSP and a GPU, buried somewhere in their PC, phone, car, etc. Most don't know or care that they bought any of these, but they did.
Will everyone, at some future point, also buy an FPGA? The market size of FPGAs today is about 1% of the annual global semiconductor sales (~$3B vs ~$300B). Will FPGA eventually...
VHDL tutorial - part 2 - Testbench
In an earlier article I walked through the VHDL coding of a simple design. In this article I will continue the process and create a test bench module to test the earlier design. The Xilinx ISE environment makes it pretty easy to start the testing process. To start the process, select "New Source" from the menu items under "Project". This launches the "New Source Wizard". From within the Wizard select "VHDL Test Bench" and enter the name of the new module (click 'Next' to...
StrangeCPU #1. A new CPU
Summary: In this multi-part series I will share with you a design, implementation notes and code for a slightly different kind of a CPU featuring a novel token machine that resolves an 8-bit token to pretty much any address in a 32-bit or even 64-bit address space, using not much more than an adder.
Table of Contents:- Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes.
VHDL tutorial
When I was first introduced to "Programmable Logic" several years ago, it was an answer to many of the challenges that I was struggling with. Though the parts were primitive by today's standards (simple PALs verses FPGA), they were an extremely cost effective tool addressing the need for specialized logic blocks.
I have continued to incorporate these powerful blocks into many of my latest designs. My current favorite part line is the Xilinx CoolRunner series (XC2Cxxx). In this...
MyHDL FPGA Tutorial I (LED Strobe)
Last updated 05-Nov-2015
IntroductionFrom many perspectives the latest FPGA offerings from 'X' and 'A' are large devices - mucho programmable logic resources. Even the devices that one can get for sub \$10 are relatively large. Because of the size of these FPGAs they are implemented using an HDL. To manually configure each circuit would be a long and tedious task. It is not feasible to program an FPGA by manually defining the logic for each LUT and manually...
VHDL tutorial - A practical example - part 2 - VHDL coding
In part 1 of this series we focused on the hardware design, including some of the VHDL definitions of the I/O characteristics of the CPLD part. In part 2, we will describe the VHDL logic of the CPLD for this design.
With any design, the first step to gather the requirements for the job at hand. From part 1 of this article, I have copied two sections that address some of the requirements for the CPLD design.
The data acquisition engine has the...
VHDL tutorial - Creating a hierarchical design
In earlier blog entries I introduced some of the basic VHDL concepts. First, developing a function ('VHDL tutorial') and later verifying and refining it ('VHDL tutorial - part 2 - Testbench' and 'VHDL tutorial - combining clocked and sequential logic'). In this entry I will describe how to...
Back from Embedded World 2019 - Funny Stories and Live-Streaming Woes
When the idea of live-streaming parts of Embedded World came to me, I got so excited that I knew I had to make it happen. I perceived the opportunity as a win-win-win-win.
- win #1 - Engineers who could not make it to Embedded World would be able to sample the huge event,
- win #2 - The organisation behind EW would benefit from the extra exposure
- win #3 - Lecturers and vendors who would be live-streamed would reach a (much) larger audience
- win #4 - I would get...
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.
Fig 1. Making a Transmission Line, with the Circuit Emulator
Additional...
A New Related Site!
We are delighted to announce the launch of the very first new Related site in 15 years! The new site will be dedicated to the trendy and quickly growing field of Machine Learning and will be called - drum roll please - MLRelated.com.
We think MLRelated fits perfectly well within the “Related” family, with:
- the fast growth of TinyML, which is a topic of great interest to the EmbeddedRelated community
- the use of Machine/Deep Learning in Signal Processing applications, which is of...
The DSP Online Conference - Right Around the Corner!
It is Sunday night as I write this blog post with a few days to go before the virtual doors of the very first DSP Online Conference open..
It all started with a post in the DSPRelated forum about three months ago. We had just had a blast running the 2020 Embedded Online Conference and we thought it could be fun to organize a smaller event dedicated to the DSP community. So my goal with the post in the forum was to see if...
Already 3000+ Attendees Registered for the Upcoming Embedded Online Conference
Chances are you already know, through the newsletter or banners on the Related sites, about the upcoming Embedded Online Conference.
Chances are you also already know that you have until the end of the month of February to register for free.
And chances are that you are one of the more than 3000 pro-active engineers who have already registered.
But If you are like me and have a tendency to do tomorrow what can be done today, maybe you haven't registered yet. You may...
Free Goodies from Embedded World - Full Inventory and Upcoming Draw Live-Streaming Date
Chances are that you already know that I went to Embedded World a few weeks ago and came back with a bag full of "goodies". Initially, my vision was to do a single draw for one person to win it all, but I didn't expect to come back with so much stuff and so many development kits. Based on your feedback, it seems like you guys agree that It wouldn't make sense for one person to win everything as no-one could make good use of all the boards and there would be lots of...
Free Goodies from Embedded World - What to Do Next?
I told you I would go on a hunt for free stuff at Embedded World in order to build a bundle for someone to win.
Back from Embedded World 2019 - Funny Stories and Live-Streaming Woes
When the idea of live-streaming parts of Embedded World came to me, I got so excited that I knew I had to make it happen. I perceived the opportunity as a win-win-win-win.
- win #1 - Engineers who could not make it to Embedded World would be able to sample the huge event,
- win #2 - The organisation behind EW would benefit from the extra exposure
- win #3 - Lecturers and vendors who would be live-streamed would reach a (much) larger audience
- win #4 - I would get...
Spread the Word and Run a Chance to Win a Bundle of Goodies from Embedded World
Do you have a Twitter and/or Linkedin account?
If you do, please consider paying close attention for the next few days to the EmbeddedRelated Twitter account and to my personal Linkedin account (feel free to connect). This is where I will be posting lots of updates about how the EmbeddedRelated.tv live streaming experience is going at Embedded World.
The most successful this live broadcasting experience will be, the better the chances that I will be able to do it...
Launch of EmbeddedRelated.tv
With the upcoming Embedded Word just around the corner, I am very excited to launch the EmbeddedRelated.tv platform.
This is where you will find the schedule for all the live broadcasts that I will be doing from Embedded World next week. Please note that the schedule will be evolving constantly, even during the show, so I suggest your refresh the page often. For instance, I am still unsure if I will be able to do the 'opening of the doors' broadcast as...
Live Streaming from Embedded World!
For those of you who won't be attending Embedded World this year, I will try to be your eyes and ears by video streaming live from the show floor.
I am not talking improvised streaming from a phone, but real, high quality HD streaming with a high-end camera and a device that will bond three internet connections (one wifi and two cellular) to ensure a steady, and hopefully reliable, stream. All this to hopefully give those of you who cannot be there in person a virtual...
