Welcoming MANY New Bloggers!
The response to the latest call for bloggers has been amazing and I am very grateful.
In this post I present to you the individuals who, so far (I am still receiving applications at an impressive rate and will update this page as more bloggers are added), have been given access to the blogging interface. I am very pleased with the positive response and I think the near future will see the publication of many great articles, given the quality of the...
Recruiting New Bloggers!
Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,
Summer of Gateware
This (last) summer the MyHDL project participated in the Google Summer of Code (GSoC) as a sub-organization under the Python Software Foundation (PSF). This was our first year participating - there was a lot for us to learn. Overall it was a worthwhile and beneficial activity.
Being a first time sub-org we were limited to a maximum of two students. We had nine students apply and twelve mentors volunteer. Only being able to select two students...
Tools of the Trade: reading PDFs (and keeping bookmarks)
In this article I will take a look at the wonderful MuPDF viewer and present a small modification that saves bookmarks alongside the pdf files, making it infinitely more useful.
Some days I sit down to work and wonder how anything ever gets done. A simple example. When I work on an FPGA design, I wind up with 3 or 4 screens full of documentation, generally in PDF format. There are the Xilinx manuals, the various tool manuals, language reference manuals, you name it. While...
Inside the Spartan-6: Using LUTs to optimize circuits
While building a small CPU on a Spartan-6 chip I came across the same old problem: my Verilog was mapping to a lot of slices . Way more then seems reasonable. So let's dig in and see what's really going on.
The J1 CPU (see Messing Around with a J1) is an amazingly streamlined design expressed in just over 100 lines of Verilog, and is reasonably compact at 150 Spartan-6 slices (half of that with the modifications described in the article). But the Picoblaze is...
Homebrew CPUs: Color Languages
Color LanguagesHere on bizarro we program using -- get this – text! Our other senses - hearing, touch, smell, are not used at all. Even our visual perception is greatly underutilized - we just use two-dimensional text on a flat display a foot in front of our eyes.
Color is just beginning to be used, although in a lame syntax coloring way only. Granted, it makes it easier to detect stupid syntax errors such as misspelled keywords. Sadly, color carries zero semantic or...
Homebrew CPUs: Messing around with a J1
In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster. I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.
J1 CPUMy hat is off to James Bowman. J1 is pretty cool. It is a stack machine; it executes instructions in one cycle, it is...
Makefiles for Xilinx Tools
Building a bitstream from an HDL is a complicated process that requires the cooperation of a lot of tools. You can hide behind an IDE or grow a pair and use command line tools and a makefile to tie your build process together. I am not a huge fan of makefiles either (I believe a language should be expressive enough to automate the build process), but the alternatives are dismal.
Command-line driven workflow is easier on the hands and faster. The example...
Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines
Introduction
This article will describe a synthesizable HDL-based microprogram controller (MPC), or microprogram sequencer (MPS), that can be used to provide the control of a microprogrammed state machine. Unlike the microprogrammed state machines that I described in my previous two articles, "Use Microprogramming to Save Resources and Add Functionality" and "Fit Sixteen (or more) Asynchronous Serial Receivers in the Area of a Standard UART", many microprogrammed state machines will...
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
IntroductionThis article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.
To stay true to the original design, I...
Verilog vs VHDL
Introduction
Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...
How precise is my measurement?
Some might argue that measurement is a blend of skepticism and faith. While time constraints might make you lean toward faith, some healthy engineering skepticism should bring you back to statistics. This article reviews some practical statistics that can help you satisfy one common question posed by skeptical engineers: “How precise is my measurement?” As we’ll see, by understanding how to answer it, you gain a degree of control over your measurement time.
An accurate, precise...Half-band filter on Xilinx FPGA
1. DSP48 Slice in Xilinx FPGA
There are many DSP48 Slices in most Xilinx® FPGAs, one DSP48 slice in Spartan6® FPGA is shown in Figure 1, the structure may different depending on the device, but broadly similar.
Figure 1: A whole DSP48A1 Slice in Spartan6 (www.xilinx.com)
2. Symmetric Systolic Half-band FIRFigure 2: Symmetric Systolic Half-band FIR Filter
3. Two-channel Symmetric Systolic Half-band FIRFigure 3: 2-Channel...
New Comments System (please help me test it)
I thought it would take me a day or two to implement, it took almost two weeks...
But here it is, the new comments systems for blogs, heavily inspired by the forum system I developed earlier this year.
Which means that:
- You can easily add images, either by drag and drop or through the 'Insert Image' button
- You can add MathML, TeX and ASCIImath equations and they will be rendered with Mathjax
- You can add code snippets and they will be highlighted with highlights.js
- You can edit...
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
IntroductionThis article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.
To stay true to the original design, I...
PC and SP for a small CPU
Ok, let's make a small stack-based CPU.
I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.
Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...
Choosing an Implementation Approach
What one man can do, another can do!--The Edge (1997) Choose the hill you want to die on.--Common saying attributed to the United States Marine Corps Planning out an FPGA Implementation
In my first article, I gave a high-level view of the project that brings me into the world of FPGA development. At the end, I tried to break down the areas of development that would be involved, and some of the knowledge and expertise I would probably have to gain in order to make it a...
Went 280km/h (174mph) in a Porsche Panamera in Germany!
Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos. It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.
How to start in FPGA development? - Simulation software tools
Introduction
This post is related to the first post How to start in FPGA development? - Some tips which aimed to show other options to work on the simulation of your project. In this first approach will be explained some advantages and disadvantages of using Xilinx ISE (+ModelSim) or using ModelSim, Precision and Xilinx ISE. And finally my opinion of which are the ones I...
Designing Embedded System with FPGA - 1
With the introduction of soft processors and related tools (like EDK from Xilinx), implementation of basic embedded system in FPGA is made easy. This requires very little or almost no knowledge of VHDL programming. Actually that’s how I started. If user is interested in taking full advantage of FPGA and its parallel processing power, then yes, detail understanding of soft processor, its peripheral bus and VHDL programming is required.
I will start with...
FPGA Assemblers and Time Machines
Flashback to 1986. A young man has a crazy idea - he wants to make a CPU all by himself. He is reading early Xilinx manuals cover to cover as if they were novels. Yes, you are quick - this is indeed a (mostly) true story about me and my dream, suddenly made possible by this new FPGA technology.
Sadly more than 20 years went by before my first CPU ran in a Xilinx FPGA. Why did it take so long? Every few years I set up the tools and every time I walked away, scared silly. As the years...
Embedded World 2018 - More Videos!
After the interview videos last week, this week I am very happy to release two more videos taken at Embedded World 2018 and that I am proud of.
For both videos, I made extensive use of my two new toys, a Zhiyun Crane Gimbal and a Sony a6300 camera.
The use of a gimbal like the Zhiyun makes a big difference in terms of making the footage look much more stable and cinematographic.
As for the Sony camera, it takes fantastic slow-motion footage and...
MyHDL Resources and Projects
Last updated 07-Nov-2017
MyHDL ResourcesIf you want to dive into MyHDL (digital hardware description in Python) there are many resources available. Below is a list of MyHDL resources, including some of the past blogs here on fpgarelated.
The MyHDL manual is a great (probably the best) place to get started.
The manual is an in-depth introduction to MyHDL. The concepts are well explained and there are examples to test while working through the...
Crowdfunding Articles?
Many of you have the knowledge and talent to write technical articles that would benefit the EE community. What is missing for most of you though, and very understandably so, is the time and motivation to do it.
But what if you could make some money to compensate for your time spent on writing the article(s)? Would some of you find the motivation and make the time?
I am thinking of implementing a system/mechanism that would allow the EE community to...
binary hello world
Python + Ohio + MyHDL + FPGARecently I had the opportunity to coordinate a hands-on programmable hardware (FPGA) workshop (open-space) at a regional Python conference - @pyohio. The workshop was for those that had little to no exposure to programmable hardware. For this situation I used two basic examples: two versions of a binary hello world.
The binary hello world -- blinking an LED -- is a good starting point to introduce programmable hardware, hardware descriptions languages,...
Back from ESC Boston
NOT going to ESC Boston would have allowed me to stay home, in my comfort zone.
NOT going to ESC Boston would have saved me from driving in the absolutely horrible & stressful Boston traffic1.
NOT going to ESC Boston would have saved me from having to go through a full search & questioning session at the Canada Customs on my return2.
2017/06/06 update: Videos are now up!So two days...
Data Types for Control & DSP
There's a lot of information out there on what data types to use for digital signal processing, but there's also a lot of confusion, so the topic bears repeating.
I recently posted an entry on PID control. In that article I glossed over the data types used by showing "double" in all of my example code. Numerically, this should work for most control problems, but it can be an extravagant use of processor resources. There ought to be a better way to determine what precision you need...
Welcoming MANY New Bloggers!
The response to the latest call for bloggers has been amazing and I am very grateful.
In this post I present to you the individuals who, so far (I am still receiving applications at an impressive rate and will update this page as more bloggers are added), have been given access to the blogging interface. I am very pleased with the positive response and I think the near future will see the publication of many great articles, given the quality of the...
SEGGER's 25th Anniversary Video
Chances are you will find this video more interesting to watch if you take five minutes to first read the story of the week I spent at SEGGER's headquarters at the end of June.
The video is only a little more than 2 minutes long. If you decide to watch it, make sure to go full screen and I would really love to read your thoughts about it in the comments down bellow. Do you think a video like this succeeds in making the viewer want to learn more about the company?...
Makefiles for Xilinx Tools
Building a bitstream from an HDL is a complicated process that requires the cooperation of a lot of tools. You can hide behind an IDE or grow a pair and use command line tools and a makefile to tie your build process together. I am not a huge fan of makefiles either (I believe a language should be expressive enough to automate the build process), but the alternatives are dismal.
Command-line driven workflow is easier on the hands and faster. The example...
