Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
This article digs into practical sampled-data issues you must address when building feedback controllers for circuit emulation. It highlights a common MATLAB versus Simulink discrepancy caused by DAC holding, explains why FOH (ramp-invariant) c2d conversion matters, and surveys latency, bit depth, filter and precision trade-offs. It also lists candidate ADCs, DACs and FPGAs used in a real evaluation platform to guide hardware choices.
Finally got a drone!
Stephane Boucher finally bought a DJI Phantom 4 and found it does more than boost his video production value, it’s also hugely fun to fly. He used the drone for an aerial shot at SEGGER’s anniversary and for a beach project where kids drew a turtle while a separate camera captured a side timelapse. The post highlights creative shot combinations and a reminder to fly where it is legal.
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
An engineer's guide to building ideal continuous-time models for hardware emulation, using TINA Spice, MATLAB and Simulink to validate controller and circuit behavior. The article shows how a passive R-C network can be emulated by an amplifier, a current measurement and a summer, with Spice, MATLAB and Simulink producing coincident Bode responses. Small phase differences between MATLAB and Simulink are noted, and sampled-data issues are slated for the next installment.
Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
This first post kicks off a series on using DSP and feedback control with mixed-signal electronics and FPGAs to emulate two-terminal circuits and create low latency controllers. It frames circuit emulation as a feedback problem, highlights latency as the key practical constraint, and outlines the planned evaluation hardware, target devices, and software tools that will be used in later MATLAB/Simulink and FPGA work.
SEGGER's 25th Anniversary Video
Stephane Boucher spent a week at SEGGER's headquarters and distilled that visit into a tight, two-minute 25th anniversary video. The post highlights rising production value, thanks to softbox lighting and a two-camera setup that allows seamless wide-to-tight cuts and emotional close-ups. Stephane invites readers to watch full screen, leave feedback and thumbs-up on YouTube, and suggests future coverage like product launches or companies with happy engineers.
Linear Feedback Shift Registers for the Uninitiated, Part II: libgf2 and Primitive Polynomials
Last time, we looked at the basics of LFSRs and finite fields formed by the quotient ring \( GF(2)[x]/p(x) \).
LFSRs can be described by a list of binary coefficients, sometimes referred as the polynomial, since they correspond directly to the characteristic polynomial of the quotient ring.
Today we’re going to look at how to perform certain practical calculations in these finite fields. I maintain a Python library called libgf2,...
Went 280km/h (174mph) in a Porsche Panamera in Germany!
Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos. It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.
Linear Feedback Shift Registers for the Uninitiated, Part I: Ex-Pralite Monks and Finite Fields
Jason Sachs demystifies linear feedback shift registers with a practical, bitwise view and the algebra that explains why they work. Readable examples compare Fibonacci and Galois implementations, show a simple software implementation, and reveal the correspondence between N-bit Galois LFSRs and GF(2^N) so you can pick taps and reason about maximal-length pseudorandom sequences.
Going back to Germany!
A couple of blog posts ago, I wrote that the decision to go to ESC Boston ended up being a great one for many different reasons. I came back from the conference energized and really happy that I went.
These feelings were amplified a few days after my return when I received an email from Rolf Segger, the founder of SEGGER Microcontroller (check out their very new website), asking if I would be interested in visiting their headquarters...
ESC Boston's Videos are Now Up
In my last blog, I told you about my experience at ESC Boston and the few videos that I was planning to produce and publish. Here they are, please have a look and any feedback (positive or negative) is appreciated.
Short HighlightThis is a very short (one minute) montage of some of the footage that I shot at the show & conference. In future shows, I absolutely need to insert clips here and there of engineers saying a few words about the conference (why they...
Shared-multiplier polyphase FIR filter
One multiplier and a dual-port RAM can implement an arbitrary m/n polyphase FIR resampler on an FPGA, Markus Nentwig demonstrates. The post focuses on practical implementation details, including a parametrized Verilog design, pipelined MAC control, and a Matlab testbench for verification. It shows how bank indexing and pipeline delay compensation let you multiplex many coefficient banks efficiently for resource-constrained FPGA designs.
Mastering Modern FPGA Skills for Engineers
In the rapidly evolving tech industry, engineers must acquire proficiency in modern FPGA skills. These skills empower engineers to optimize designs, minimize resource usage, and efficiently address FPGA design challenges while ensuring functionality, security, and compliance.
Jumping from MCUs to FPGAs - 5 things you need to know
Are you a microcontroller expert beckoned by the siren song of the FPGA? Not long ago, that was me. FPGA-expert friends of mine regularly extolled the virtues of these mysterious components and I wanted in. When I made the leap, I found a world seemingly very familiar, but in reality, vastly different. I found that my years of C programming and microcontroller use often gave pre preconceived interpretations of FPGA resource material which resulted in eye-roll class mistakes in my code. I’ve gleaned five things of vital importance to help you make that transition faster than I did.
Back from ESC Boston
Stephane nearly skipped ESC Boston, but going turned into a productive mix of networking, informal meetups, and on-the-floor filming. He captures candid encounters with speakers and vendors, learns how small shows differ from larger expos, and outlines practical follow-ups like booth highlight videos and speaker hospitality suggestions. The post is an encouraging read for engineers weighing the value of regional conferences and DIY event coverage.
Running Average
This post shows a lightweight running average variant that cleans up noisy wheel-encoder timing using a shift-based divide-by-8 and a small rounding constant. The filter updates as M1 = M0 + (t0 - A0), where A0 is estimated from the previous average, so each new measurement nudges the estimate rather than immediately replacing it. It trades exact oldest-sample subtraction for low resource cost and strong noise suppression.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
Spread the Word and Run a Chance to Win a Bundle of Goodies from Embedded World
Do you have a Twitter and/or Linkedin account?
If you do, please consider paying close attention for the next few days to the EmbeddedRelated Twitter account and to my personal Linkedin account (feel free to connect). This is where I will be posting lots of updates about how the EmbeddedRelated.tv live streaming experience is going at Embedded World.
The most successful this live broadcasting experience will be, the better the chances that I will be able to do it...
Homebrew CPUs: Messing around with a J1
Victor Yurkovsky takes James Bowman's compact J1 stack CPU and starts hacking: he trims the ALU, replaces the barrel shifter with simpler shifts, and experiments with dual stacks and memory/IO feeding directly into the ALU. The article walks through small, practical changes that cut logic, add instructions, and boost timing on Spartan-6. It's a hands-on tour that shows how approachable homebrew CPUs can be.
The Spartans
Christopher Felton walks through the Spartan6 FPGA basics, explaining CLBs, slices, and the new 6-input LUTs while comparing them to Spartan3. He ran timing-driven mappings of real gateware to show practical LUT utilization differences. The post gives a pragmatic estimate of expected LUT savings and points out where mapping results can vary depending on the design.
Sensors Expo - Trip Report & My Best Video Yet!
Stephane Boucher turns a first-time Sensors Expo visit into a fun travelogue and a polished conference highlights video. He mixes candid trip anecdotes from Moncton to San Jose, electric-scooter discoveries, Santa Cruz detours, Airbnb tips, and on-the-floor expo footage. The post culminates in what he calls his best highlights reel yet, plus a follow-up video focused on embedded and IoT.
StrangeCPU #3. Instruction Slides - The Strangest CPU Yet!
Victor Yurkovsky extends his sliding-window token machine idea to instruction decoding, showing how 8/9-bit tokens can index shared "Blue" memory as 32-bit literals, call targets, or decoded instructions. The approach makes instructions dynamic entries that slide with the window, enabling rare opcodes to be synthesized on demand and reducing fixed opcode bloat. He also covers the 0-bit window (the stack), FPGA BRAM tagging, and the latency trade-offs.
Square root in fixed point VHDL
In this blog we will design and implement a fixed point square root function in VHDL. The algorithm is based on the recursive Newton Raphson inverse square root algorithm and the implementation offers parametrizable pipeline depth, word length and the algorithm is built with VHDL records and procedures for easy use.
Inside the Spartan-6: Using LUTs to optimize circuits
Victor Yurkovsky hit poor synthesis packing while building a J1 CPU on Spartan-6 and traced the problem to an 18-bit logic ALU that mapped to many slices. He demonstrates a practical fix: instantiate LUT6 primitives with carefully chosen INIT values, then use RLOC placement to stack the per-bit LUTs and collapse the design down to five slices. This is a hands-on guide to Xilinx-specific optimization when synthesis falls short.
PC and SP for a small CPU
Victor Yurkovsky walks through a compact stack-based CPU idea that tosses the conventional PC register in favor of a return stack living in Xilinx distributed RAM. The clever twist uses the stack memory addressed by SP as the program counter, making calls trivial and keeping the design tiny. The article shows the Verilog stack module and explains the practical tradeoffs of isolating the return stack.
Linear Feedback Shift Registers for the Uninitiated, Part II: libgf2 and Primitive Polynomials
Last time, we looked at the basics of LFSRs and finite fields formed by the quotient ring \( GF(2)[x]/p(x) \).
LFSRs can be described by a list of binary coefficients, sometimes referred as the polynomial, since they correspond directly to the characteristic polynomial of the quotient ring.
Today we’re going to look at how to perform certain practical calculations in these finite fields. I maintain a Python library called libgf2,...
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
Running Average
This post shows a lightweight running average variant that cleans up noisy wheel-encoder timing using a shift-based divide-by-8 and a small rounding constant. The filter updates as M1 = M0 + (t0 - A0), where A0 is estimated from the previous average, so each new measurement nudges the estimate rather than immediately replacing it. It trades exact oldest-sample subtraction for low resource cost and strong noise suppression.
Spline interpolation
Markus Nentwig provides a cookbook for segmented cubic spline interpolation that turns scattered or noisy data into efficient fixed-point functions. The article shows how to build third-order polynomial segments with explicit value and slope control via basis functions, solve scaling factors by least-squares in Octave/Matlab, and export coefficients for Verilog RTL evaluation using the Horner scheme and practical fixed-point tips.
Verilog vs VHDL
Muhammad Yasir compares Verilog and VHDL by tracing their history, core features, and global usage to help engineers pick an HDL. The post explains where each language shines: Verilog for concise, low-level IC modeling and faster coding, VHDL for strong typing, packages, and system-level clarity, and it uses Google Trends and market examples to put adoption into context.
Welcoming MANY New Bloggers!
A big influx of new voices just joined DSPRelated, and Stephane Boucher introduces the growing roster of contributors and their backgrounds. The post lists dozens of newly approved bloggers, highlights the range of DSP and embedded expertise they bring, and asks readers to leave constructive feedback on posts. It also explains why some applicants may not have been accepted yet and how to apply properly.
