Embedded World 2018 - More Videos!
After the interview videos last week, this week I am very happy to release two more videos taken at Embedded World 2018 and that I am proud of.
For both videos, I made extensive use of my two new toys, a Zhiyun Crane Gimbal and a Sony a6300 camera.
The use of a gimbal like the Zhiyun makes a big difference in terms of making the footage look much more stable and cinematographic.
As for the Sony camera, it takes fantastic slow-motion footage and...
Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed
This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the design and evaluation of specific controllers and closed-loop applications.
Additional design...Embedded World 2018 - The Interviews
Once again this year, I had the chance to go to Embedded World in Nuremberg Germany. And once again this year, I brought my video equipment to try and capture some of the most interesting things at the show.
Something new this year, I asked Jacob Beningo if he would partner with me in doing interviews with a few vendors. I would operate the camera while Jacob would ask the right questions to the vendors to make them talk about the key products/features that...
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator
Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.
This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.
- Part 6: Self-Calibration, Measurements and Signalling (this part)
- Part 5:
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with application examples will be maintained on the project website here.- Part 5: Some FPGA Aspects (this part)
- Part 4: Engineering of...
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...
Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
Some Design and Simulation Considerations for Sampled-Data ControllersThis article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to sampled-data systems.
- Part 1: Introduction
Finally got a drone!
As a reader of my blog, you already know that I have been making videos lately and thoroughly enjoying the process. When I was in Germany early this summer (and went 280 km/h in a porsche!) to produce SEGGER's 25th anniversary video, the company bought a drone so we could get an aerial shot of the party (at about the 1:35 mark in this video). Since then, I have been obsessing on buying a drone for myself and finally made the move a few weeks ago - I acquired a used DJI...
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
Developing and Validating Simulation ModelsThis article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.
- Part 1: Introduction
- Part 2: Ideal Model Examples
- Part 3: Sampled Data Aspects
- Part 4: Engineering of Evaluation Hardware
- Part 5:
The Ice is Broken
When I suggested that you lower you expectations before watching my first live session, I wasn't kidding.
Still, I was hoping I would do much better than what I had prepared you for but obviously it wasn't meant to be.
Don't get me wrong, a few things went very well, like the technical aspects for instance. I thought the improvised studio looked pretty good, the audio sounded fine and the HD stream was nice and steady.
And my mom thinks that I looked handsome...
A Balancing Act
For the second live streaming session, I give myself a 5/10.
I felt much more comfortable and was way better prepared than when I did my first session - and that's why I went from 3/10 to 5/10 in my system of self-awarded rating - but my attempt at 'live' humor fell rather flat I think and I had some technical difficulties with the live streaming itself. So I believe 5/10 is fair and leaves lots of room for improvement.
As far as my attempt at humor is concerned, you...
VHDL tutorial - combining clocked and sequential logic
In an earlier article on VHDL programming ("VHDL tutorial" and "VHDL tutorial - part 2 - Testbench", I described a design for providing a programmable clock divider for a ADC sequencer. In this example, I showed how to generate a clock signal (ADCClk), that was to be programmable over a series of fixed rates (20MHz, 10MHz, 4MHz, 2MHz, 1MHz and 400KHz), given a master clock rate of 40MHz. A reader of that article had written to ask if it was possible to extend the design to...
Homebrew CPUs: Messing around with a J1
In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster. I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.
J1 CPUMy hat is off to James Bowman. J1 is pretty cool. It is a stack machine; it executes instructions in one cycle, it is...
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
This article will look at a design approach for feedback controllers featuring low-latency "irrational" characteristics to enable the creation of physical components such as transmission lines. Some thought will also be given as to the capabilities of the currently utilized Intel Cyclone V, the new Cyclone 10 GX and the upcoming Xilinx Versal floating-point FPGAs/ACAPs.
Fig 1. Making a Transmission Line, with the Circuit Emulator
Additional...
Inside the Spartan-6: Using LUTs to optimize circuits
While building a small CPU on a Spartan-6 chip I came across the same old problem: my Verilog was mapping to a lot of slices . Way more then seems reasonable. So let's dig in and see what's really going on.
The J1 CPU (see Messing Around with a J1) is an amazingly streamlined design expressed in just over 100 lines of Verilog, and is reasonably compact at 150 Spartan-6 slices (half of that with the modifications described in the article). But the Picoblaze is...
Makefiles for Xilinx Tools
Building a bitstream from an HDL is a complicated process that requires the cooperation of a lot of tools. You can hide behind an IDE or grow a pair and use command line tools and a makefile to tie your build process together. I am not a huge fan of makefiles either (I believe a language should be expressive enough to automate the build process), but the alternatives are dismal.
Command-line driven workflow is easier on the hands and faster. The example...
Discrete-Time PLLs, Part 1: Basics
Design Files: Part1.slx
Hi everyone,
In this series of tutorials on discrete-time PLLs we will be focusing on Phase-Locked Loops that can be implemented in discrete-time signal proessors such as FPGAs, DSPs and of course, MATLAB.
In the first part of the series, we will be reviewing the basics of continuous-time baseband PLLs and we will see some useful mathematics that will give us insight into the inners working of PLLs. In the second part, we will focus on...
Shared-multiplier polyphase FIR filter
Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier
Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.
IntroductionA polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...
Lower your Expectations
This Friday, I will for the first time be the person in front of the camera, the star of my own show on EmbeddedRelated.tv. I will be experimenting with talking live to the *Related sites community, using the 'Free Goodies' prize draw as a pretext.
This could become a very effective way to communicate with you and part of me is genuinely excited and really looking forward to go live.
But there is another part of me that is slightly...
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Introduction
There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency oscillator on the leading edge of the 1PPS signal. In many cases, this will result in adequate performance. However, in situations where simple synchronization does not provide adequate performance, digital phase-lock techniques can be applied to a...
Verilog vs VHDL
Introduction
Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...
Introduction to FPGA Technology
OverviewFPGA stands for Field Programmable Gate Array. An FPGA is an integrated circuit (IC) that can be programmed and configured by the embedded system developer in the field after it has been manufactured. FPGA is a semi-conductor device which is not limited to any pre-defined hardware function; it is rather highly flexible in its functionality and may be configured by the embedded system developer according to his design requirements. FPGAs use pre-built logic blocks and programmable...
Little to no benefit from C based HLS
Last updated 07-Nov-2015
As I write this I am on a plane and my destination is EELive 2014 where I am going to give a talk hardware design: the grunge era. It is a shotgun introduction to three alternative hardware description languages (alt.hdl). The three languages briefly introduced in the talk are: bsv, chisel, and myhdl. The goal of the talk is simply to raise awareness of the three...
PC and SP for a small CPU
Ok, let's make a small stack-based CPU.
I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.
Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...
Signed serial-/parallel multiplication
Keywords: Binary signed multiplication implementation, RTL, Verilog, algorithm
Summary- A detailed discussion of bit-level trickstery in signed-signed multiplication
- Algorithm based on Wikipedia example
- Includes a Verilog implementation with parametrized bit width
A straightforward method to multiply two binary numbers is to repeatedly shift the first argument a, and add to a register if the corresponding bit in the other argument b is set. The...
Recruiting New Bloggers!
Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption. Public Key encryption is used to create a private key between two sides that have not previously communicated. Compared to the history of encryption, Public Key methods are very recent having been started in the 1970's. Elliptic...
Linear Feedback Shift Registers for the Uninitiated, Part I: Ex-Pralite Monks and Finite Fields
Later there will be, I hope, some people who will find it to their advantage to decipher all this mess.
— Évariste Galois, May 29, 1832
I was going to call this short series of articles “LFSRs for Dummies”, but thought better of it. What is a linear feedback shift register? If you want the short answer, the Wikipedia article is a decent introduction. But these articles are aimed at those of you who want a little bit deeper mathematical understanding,...
Homebrew CPUs: Messing around with a J1
In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster. I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.
J1 CPUMy hat is off to James Bowman. J1 is pretty cool. It is a stack machine; it executes instructions in one cycle, it is...
Back from ESC Boston
NOT going to ESC Boston would have allowed me to stay home, in my comfort zone.
NOT going to ESC Boston would have saved me from driving in the absolutely horrible & stressful Boston traffic1.
NOT going to ESC Boston would have saved me from having to go through a full search & questioning session at the Canada Customs on my return2.
2017/06/06 update: Videos are now up!So two days...
Launch of Youtube Channel: My First Videos - Embedded World 2017
I went to Embedded World 2017 in Nuremberg with an ambitious plan; I would make video highlights of several exhibits (booths) to be presented to the *Related sites audience. I would try to make the vendors focus their pitch on the essential in order to produce a one to three minutes video per booth.
So far my experience with making videos was limited to family videos, so I knew I had lots of reading to do and lots of Youtube videos and tutorials to watch. Trade shows are...
New Comments System (please help me test it)
I thought it would take me a day or two to implement, it took almost two weeks...
But here it is, the new comments systems for blogs, heavily inspired by the forum system I developed earlier this year.
Which means that:
- You can easily add images, either by drag and drop or through the 'Insert Image' button
- You can add MathML, TeX and ASCIImath equations and they will be rendered with Mathjax
- You can add code snippets and they will be highlighted with highlights.js
- You can edit...
3 Good News
Good News #1Last week, I announced a new and ambitious reward program that will be funded by the new Vendors Directory.
This week, I am happy to announce that we have our firsts two sponsors! Quantum Leaps & Abelon Systems have agreed to pay the sponsorship fee to be listed in the new Vendors Directory. Because of their support, there is now some money in the reward pool ($1,000) and enough to pay for the firsts 500 'beers' awarded. Please...
The New Forum is LIVE!
After months of hard word, I am very excited to introduce to you the new forum interface.
Here are the key features:
1- Easily add images to a post by drag & dropping the images in the editor
2- Easily attach files to a post by drag & dropping the files in the editor
3- Add latex equations to a post and they will be rendered with Mathjax (tutorial)
4- Add a code snippet and surround the code with
Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!
Breaking the ice can be tough. Over the years, many individuals have asked to be given access to the blogging interface only to never post an article. Maybe they underestimated the time it takes to write a decent article, or maybe they got cold feet. I don't blame or judge them at all - how many times in my life have I had the intention to do something but didn't follow through? Once, maybe twice 😉 (don't worry if you don't...
Welcoming MANY New Bloggers!
The response to the latest call for bloggers has been amazing and I am very grateful.
In this post I present to you the individuals who, so far (I am still receiving applications at an impressive rate and will update this page as more bloggers are added), have been given access to the blogging interface. I am very pleased with the positive response and I think the near future will see the publication of many great articles, given the quality of the...
Recruiting New Bloggers!
Previous calls for bloggers have been very successful in recruiting some great communicators - Rick Lyons, Jason Sachs, Victor Yurkovsky, Mike Silva, Markus Nentwig, Gene Breniman, Stephen Friederichs,
Two jobs
For those of you following closely embeddedrelated and the other related sites, you might have noticed that I have been less active for the last couple of months, and I will use this blog post to explain why. The main reason is that I got myself involved into a project that ended up using a better part of my cpu than I originally thought it would.
edit - video of the event:
I currently have two jobs: one as an electrical/dsp engineer recycled as a web publisher and the other...
FPGA Bloggers Needed - New Reward System
Are you an FPGA expert? If you are an have an interest in sharing your knowledge with the FPGA community, you might be interested in the new reward system for bloggers (see the blogs section here).
The rewards will be based on page impressions, meaning that the more traffic a blog post will get, the faster it will generate rewards for the author.
Basically, a given blog post will generate $25 to the author for every 250 unique pageviews, up to a maximum total reward of $500 per blog post...
