## Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality.

Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator

## Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.

This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.

• Part 6: Self-Calibration, Measurements and Signalling (this part)
• Part 5:

## Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

November 14, 2017
This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with  application  examples will be maintained on the project website here.

## Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware

October 10, 2017
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with  application  examples will be maintained on the project website.

## Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects

September 9, 2017
Some Design and Simulation Considerations for Sampled-Data Controllers

This article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to sampled-data systems.

## Finally got a drone!

As a reader of my blog, you already know that I have been making videos lately and thoroughly enjoying the process.  When I was in Germany early this summer (and went 280 km/h in a porsche!) to produce SEGGER's 25th anniversary video, the company bought a drone so we could get an aerial shot of the party (at about the 1:35 mark in this video).  Since then, I have been obsessing on buying a drone for myself and finally made the move a few weeks ago - I acquired a used DJI...

## Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

August 24, 2017
Developing and Validating Simulation Models

This article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.

## Feedback Controllers - Making Hardware with Firmware. Part I. Introduction

August 22, 2017
Introduction to the topic

This is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and performance of a practical design made from modestly-priced state of the art devices.

• Part 1:

## SEGGER's 25th Anniversary Video

Chances are you will find this video more interesting to watch if you take five minutes to first read the story of the week I spent at SEGGER's headquarters at the end of June.

The video is only a little more than 2 minutes long.  If you decide to watch it, make sure to go full screen and I would really love to read your thoughts about it in the comments down bellow.  Do you think a video like this succeeds in making the viewer want to learn more about the company?...

## Linear Feedback Shift Registers for the Uninitiated, Part II: libgf2 and Primitive Polynomials

July 17, 2017

Last time, we looked at the basics of LFSRs and finite fields formed by the quotient ring $GF(2)[x]/p(x)$.

LFSRs can be described by a list of binary coefficients, sometimes referred as the polynomial, since they correspond directly to the characteristic polynomial of the quotient ring.

Today we’re going to look at how to perform certain practical calculations in these finite fields. I maintain a Python library on bitbucket called...

## Use DPLL to Lock Digital Oscillator to 1PPS Signal

Introduction

There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency oscillator on the leading edge of the 1PPS signal. In many cases, this will result in adequate performance. However, in situations where simple synchronization does not provide adequate performance, digital phase-lock techniques can be applied to a...

## Introduction to FPGA Technology

May 12, 2011
Overview

FPGA stands for Field Programmable Gate Array. An FPGA is an integrated circuit (IC) that can be programmed and configured by the embedded system developer in the field after it has been manufactured. FPGA is a semi-conductor device which is not limited to any pre-defined hardware function; it is rather highly flexible in its functionality and may be configured by the embedded system developer according to his design requirements. FPGAs use pre-built logic blocks and programmable...

## Verilog vs VHDL

June 13, 2011

Introduction

Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...

## Linear Feedback Shift Registers for the Uninitiated, Part I: Ex-Pralite Monks and Finite Fields

Later there will be, I hope, some people who will find it to their advantage to decipher all this mess.

— Évariste Galois, May 29, 1832

I was going to call this short series of articles “LFSRs for Dummies”, but thought better of it. What is a linear feedback shift register? If you want the short answer, the Wikipedia article is a decent introduction. But these articles are aimed at those of you who want a little bit deeper mathematical understanding,...

## Signed serial-/parallel multiplication

February 16, 2014

Keywords: Binary signed multiplication implementation, RTL, Verilog, algorithm

Summary
• A detailed discussion of bit-level trickstery in signed-signed multiplication
• Algorithm based on Wikipedia example
• Includes a Verilog implementation with parametrized bit width
Signed serial-/parallel multiplication

A straightforward method to multiply two binary numbers is to repeatedly shift the first argument a, and add to a register if the corresponding bit in the other argument b is set. The...

## Little to no benefit from C based HLS

April 4, 2014

Last updated 07-Nov-2015

As I write this I am on a plane and my destination is EELive 2014 where I am going to give a talk hardware design: the grunge era.  It is a shotgun introduction to three alternative hardware description languages (alt.hdl). The three languages briefly introduced in the talk are: bsv, chisel, and myhdl.  The goal of the talk is simply to raise awareness of the three...

## PC and SP for a small CPU

July 23, 2013

Ok, let's make a small stack-based CPU.

I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.

Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...

## Recruiting New Bloggers!

Previous calls for bloggers have been very successful in recruiting some great communicators - Rick LyonsJason Sachs, Victor Yurkovsky, Mike Silva, Markus NentwigGene BrenimanStephen Friederichs,

## Elliptic Curve Cryptography

Secure online communications require encryption.  One standard is AES (Advanced Encryption Standard) from NIST.  But for this to work, both sides need the same key for encryption and decryption.  This is called Private Key encryption.  Public Key encryption is used to create a private key between two sides that have not previously communicated.  Compared to the history of encryption, Public Key methods are very recent having been started in the 1970's.  Elliptic...

## Homebrew CPUs: Messing around with a J1

May 29, 2015

In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster.  I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.

J1 CPU

My hat is off to James Bowman.  J1 is pretty cool.  It is a stack machine; it executes instructions in one cycle, it is...

## 3 Good News

March 9, 20161 comment
Good News #1

Last week, I announced a new and ambitious reward program that will be funded by the new Vendors Directory.