FPGARelated.com

Cutting a Path Forward

David Days April 4, 20183 comments
Introduction

As a newcomer to the community, I thought I would start off by introducing myself, and give a little information about what has drawn me to start working with FPGAs.

My day job is as a professional software developer:  Figure out what people want; figure out how to make it happen (if possible); and then wrangle code, databases, networks, and servers into giving the correct responses or actions as necessary.

By night, however, I've been working on my...


How precise is my measurement?

Sam Shearman March 28, 20183 comments

Some might argue that measurement is a blend of skepticism and faith. While time constraints might make you lean toward faith, some healthy engineering skepticism should bring you back to statistics. This article reviews some practical statistics that can help you satisfy one common question posed by skeptical engineers: “How precise is my measurement?” As we’ll see, by understanding how to answer it, you gain a degree of control over your measurement time.

An accurate, precise...

Embedded World 2018 - More Videos!

Stephane Boucher March 27, 20181 comment

After the interview videos last week, this week I am very happy to release two more videos taken at Embedded World 2018 and that I am proud of.  

For both videos, I made extensive use of my two new toys, a Zhiyun Crane Gimbal and a Sony a6300 camera.

The use of a gimbal like the Zhiyun makes a big difference in terms of making the footage look much more stable and cinematographic.

As for the Sony camera, it takes fantastic slow-motion footage and...


Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed

Steve Maslen March 21, 2018

This part in the series will consider the signals, measurements, analyses and configurations for testing high-speed low-latency feedback loops and their controllers. Along with basic test signals, a versatile IFFT signal generation scheme will be discussed and implemented. A simple controller under test will be constructed to demonstrate the analysis principles in preparation for the design and evaluation of specific controllers and closed-loop applications.

Additional design...

Embedded World 2018 - The Interviews

Stephane Boucher March 21, 2018

Once again this year, I had the chance to go to Embedded World in Nuremberg Germany.  And once again this year, I brought my video equipment to try and capture some of the most interesting things at the show.  

Something new this year, I asked Jacob Beningo if he would partner with me in doing interviews with a few vendors.  I would operate the camera while Jacob would ask the right questions to the vendors to make them talk about the key products/features that...


Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators

Steve Maslen January 5, 20187 comments
This article will look at some DSP Sine-wave oscillators and will show how an FPGA with limited floating-point performance due to latency, can be persuaded to produce much higher sample-rate sine-waves of high quality. 

Comparisons will be made between implementations on Intel Cyclone V and Cyclone 10 GX FPGAs. An Intel numerically controlled oscillator


Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.

Steve Maslen December 3, 20177 comments

This article will consider the engineering of a self-calibration & self-test capability to enable the project hardware to be configured and its basic performance evaluated and verified, ready for the development of the low-latency controller DSP firmware and closed-loop applications. Performance specifications will be documented in due course, on the project website here.

  • Part 6: Self-Calibration, Measurements and Signalling (this part)
  • Part 5:

Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.

Steve Maslen November 14, 2017
This part of the on-going series of articles looks at a variety of aspects concerning the FPGA device which provides the high-speed maths capability for the low-latency controller and the arbitrary circuit generator application. In due course a complete specification along with  application  examples will be maintained on the project website here.

Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware

Steve Maslen October 10, 2017
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with  application  examples will be maintained on the project website. 

Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects

Steve Maslen September 9, 2017
Some Design and Simulation Considerations for Sampled-Data Controllers

This article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to sampled-data systems.


Computing Fixed-Point Square Roots and Their Reciprocals Using Goldschmidt Algorithm

Michael Morris June 14, 202010 comments
Introduction

A well known algorithm for computing square roots by iteration is provided by the Newton-Raphson Algorithm. The algorithm determines the square root using iteration until the root has been determined to some user-defined level of accuracy. The method is easily derived. First, describe a number in terms of its square root:

$$ a = y ^ {2} ,$$

where $y = \sqrt{a}$. The value of the $\sqrt{a}$ can be written as $y = y_0 + \epsilon$, where $y_0$ is the value of the square root and...


Homebrew CPUs: Messing around with a J1

Victor Yurkovsky May 29, 2015

In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster.  I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.

J1 CPU

My hat is off to James Bowman.  J1 is pretty cool.  It is a stack machine; it executes instructions in one cycle, it is...


Spread the Word and Run a Chance to Win a Bundle of Goodies from Embedded World

Stephane Boucher February 21, 2019

Do you have a Twitter and/or Linkedin account?

If you do, please consider paying close attention for the next few days to the EmbeddedRelated Twitter account and to my personal Linkedin account (feel free to connect).  This is where I will be posting lots of updates about how the EmbeddedRelated.tv live streaming experience is going at Embedded World.

The most successful this live broadcasting experience will be, the better the chances that I will be able to do it...


Verilog vs VHDL

Muhammad Yasir June 13, 2011

Introduction

 

Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...


Shared-multiplier polyphase FIR filter

Markus Nentwig July 31, 20137 comments

Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier

Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.

Introduction

A polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...


PC and SP for a small CPU

Victor Yurkovsky July 23, 2013

Ok, let's make a small stack-based CPU.

I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.

Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...


Recruiting New Bloggers!

Stephane Boucher October 16, 20157 comments

Previous calls for bloggers have been very successful in recruiting some great communicators - Rick LyonsJason Sachs, Victor Yurkovsky, Mike Silva, Markus NentwigGene BrenimanStephen Friederichs,


Little to no benefit from C based HLS

Christopher Felton April 4, 2014

Last updated 07-Nov-2015

As I write this I am on a plane and my destination is EELive 2014 where I am going to give a talk hardware design: the grunge era.  It is a shotgun introduction to three alternative hardware description languages (alt.hdl). The three languages briefly introduced in the talk are: bsv, chisel, and myhdl.  The goal of the talk is simply to raise awareness of the three...


Spline interpolation

Markus Nentwig May 11, 20147 comments

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

Introduction

Splines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...


Dealing With Fixed Point Fractions

Mike January 5, 20163 comments

Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow.  If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions.  When integers overflow, they lose data off the most significant bits.  When fractions overflow, they lose data off...


New Design - Finally!

Stephane Boucher April 29, 20093 comments

For those of you who are familiar with my work, you already know that FPGARelated.com is not the only engineering web site that I publish. I also publish DSPRelated.com and EmbeddedRelated.com. Those two web sites have been on a new design for quite some time now and porting the new design to FPGARelated.com has been on my todo list for too long!  I am glad today to announce that I have finally found the time to apply the more modern design to FPGARelated.com.

Thank you...


New Discussion Group: DSP & FPGA

Stephane Boucher September 11, 20078 comments

I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to: fpgadsp-subscribe@yahoogroups.com

As usual, it should take a few weeks before there are enough members for interesting discussions to get started.