## Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects

September 9, 2017
Some Design and Simulation Considerations for Sampled-Data Controllers

This article will continue to look at some aspects of the controllers and electronics needed to create emulated physical circuits with real-world connectivity and will look at the issues that arise in sampled-data controllers compared to continuous-domain controllers. As such, is not intended as an introduction to sampled-data systems.

## Finally got a drone!

August 28, 20172 comments

As a reader of my blog, you already know that I have been making videos lately and thoroughly enjoying the process.  When I was in Germany early this summer (and went 280 km/h in a porsche!) to produce SEGGER's 25th anniversary video, the company bought a drone so we could get an aerial shot of the party (at about the 1:35 mark in this video).  Since then, I have been obsessing on buying a drone for myself and finally made the move a few weeks ago - I acquired a used DJI...

## Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples

August 24, 2017
Developing and Validating Simulation Models

This article will describe models for simulating the systems and controllers for the hardware emulation application described in Part 1 of the series.

## Feedback Controllers - Making Hardware with Firmware. Part I. Introduction

August 22, 2017
Introduction to the topic

This is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and performance of a practical design made from modestly-priced state of the art devices.

• Part 1:

## SEGGER's 25th Anniversary Video

July 18, 20172 comments

Chances are you will find this video more interesting to watch if you take five minutes to first read the story of the week I spent at SEGGER's headquarters at the end of June.

The video is only a little more than 2 minutes long.  If you decide to watch it, make sure to go full screen and I would really love to read your thoughts about it in the comments down bellow.  Do you think a video like this succeeds in making the viewer want to learn more about the company?...

## Linear Feedback Shift Registers for the Uninitiated, Part II: libgf2 and Primitive Polynomials

July 17, 2017

Last time, we looked at the basics of LFSRs and finite fields formed by the quotient ring $GF(2)[x]/p(x)$.

LFSRs can be described by a list of binary coefficients, sometimes referred as the polynomial, since they correspond directly to the characteristic polynomial of the quotient ring.

Today we’re going to look at how to perform certain practical calculations in these finite fields. I maintain a Python library on bitbucket called...

## Went 280km/h (174mph) in a Porsche Panamera in Germany!

July 10, 201712 comments

Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos.  It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.

## Linear Feedback Shift Registers for the Uninitiated, Part I: Ex-Pralite Monks and Finite Fields

July 3, 20176 comments

Later there will be, I hope, some people who will find it to their advantage to decipher all this mess.

— Évariste Galois, May 29, 1832

I was going to call this short series of articles “LFSRs for Dummies”, but thought better of it. What is a linear feedback shift register? If you want the short answer, the Wikipedia article is a decent introduction. But these articles are aimed at those of you who want a little bit deeper mathematical understanding,...

## Going back to Germany!

June 13, 20176 comments

A couple of blog posts ago, I wrote that the decision to go to ESC Boston ended up being a great one for many different reasons.  I came back from the conference energized and really happy that I went.

These feelings were amplified a few days after my return when I received an email from Rolf Segger, the founder of SEGGER Microcontroller (check out their very new website), asking if I would be interested in visiting their headquarters...

## ESC Boston's Videos are Now Up

June 5, 2017

In my last blog, I told you about my experience at ESC Boston and the few videos that I was planning to produce and publish.  Here they are, please have a look and any feedback (positive or negative) is appreciated.

Short Highlight

This is a very short (one minute) montage of some of the footage that I shot at the show & conference.  In future shows, I absolutely need to insert clips here and there of engineers saying a few words about the conference (why they...

## Verilog vs VHDL

June 13, 2011

Introduction

Verilog and VHDL are two industry standard Hardware Description Languages (HDL) that are used in writing programs for electronic integrated circuits (ICs) i.e., ASIC and FPGA. Many system designers face this issue: which HDL language to choose – Verilog or VHDL. The answer is by no means easy or trivial. Both of these languages are widely compared and contrasted without any clearly defined victor. Both of them have their own merits and demerits and have different...

## Homebrew CPUs: Messing around with a J1

May 29, 2015

In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster.  I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.

J1 CPU

My hat is off to James Bowman.  J1 is pretty cool.  It is a stack machine; it executes instructions in one cycle, it is...

## PC and SP for a small CPU

July 23, 2013

Ok, let's make a small stack-based CPU.

I will start where the rubber meets the road - the PC/stack subsystem that I like referring to as the 'legs'. As usual, I will present a design with a twist.

Not having a large design team, deadlines and million-dollar fab runs when designing CPUs creates a truly different environment. I can actually sit at the kitchen table and doodle around with CPU designs to my heart's content. I can try really ridiculous approaches, and work without a...

## Shared-multiplier polyphase FIR filter

July 31, 20136 comments

Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier

Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.

Introduction

A polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...

## Little to no benefit from C based HLS

April 4, 2014

Last updated 07-Nov-2015

As I write this I am on a plane and my destination is EELive 2014 where I am going to give a talk hardware design: the grunge era.  It is a shotgun introduction to three alternative hardware description languages (alt.hdl). The three languages briefly introduced in the talk are: bsv, chisel, and myhdl.  The goal of the talk is simply to raise awareness of the three...

## Recruiting New Bloggers!

October 16, 20157 comments

Previous calls for bloggers have been very successful in recruiting some great communicators - Rick LyonsJason Sachs, Victor Yurkovsky, Mike Silva, Markus NentwigGene BrenimanStephen Friederichs,

## Spline interpolation

May 11, 20147 comments

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

Introduction

Splines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...

## Elliptic Curve Cryptography

November 16, 20156 comments

Secure online communications require encryption.  One standard is AES (Advanced Encryption Standard) from NIST.  But for this to work, both sides need the same key for encryption and decryption.  This is called Private Key encryption.  Public Key encryption is used to create a private key between two sides that have not previously communicated.  Compared to the history of encryption, Public Key methods are very recent having been started in the 1970's.  Elliptic...

## Dealing With Fixed Point Fractions

January 5, 20163 comments

Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow.  If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions.  When integers overflow, they lose data off the most significant bits.  When fractions overflow, they lose data off...

## Went 280km/h (174mph) in a Porsche Panamera in Germany!

July 10, 201712 comments

Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos.  It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.

## New Design - Finally!

April 29, 20093 comments

For those of you who are familiar with my work, you already know that FPGARelated.com is not the only engineering web site that I publish. I also publish DSPRelated.com and EmbeddedRelated.com. Those two web sites have been on a new design for quite some time now and porting the new design to FPGARelated.com has been on my todo list for too long!  I am glad today to announce that I have finally found the time to apply the more modern design to FPGARelated.com.

Thank you...

## New Discussion Group: DSP & FPGA

September 11, 20078 comments

I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to: fpgadsp-subscribe@yahoogroups.com

As usual, it should take a few weeks before there are enough members for interesting discussions to get started.