Feedback Controllers - Making Hardware with Firmware. Part I. Introduction
Introduction to the topic
This is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and performance of a practical design made from modestly-priced state of the art devices.
- Part 1:
SEGGER's 25th Anniversary Video
Chances are you will find this video more interesting to watch if you take five minutes to first read the story of the week I spent at SEGGER's headquarters at the end of June.
The video is only a little more than 2 minutes long. If you decide to watch it, make sure to go full screen and I would really love to read your thoughts about it in the comments down bellow. Do you think a video like this succeeds in making the viewer want to learn more about the company?...
Linear Feedback Shift Registers for the Uninitiated, Part II: libgf2 and Primitive Polynomials
Last time, we looked at the basics of LFSRs and finite fields formed by the quotient ring \( GF(2)[x]/p(x) \).
LFSRs can be described by a list of binary coefficients, sometimes referred as the polynomial, since they correspond directly to the characteristic polynomial of the quotient ring.
Today we’re going to look at how to perform certain practical calculations in these finite fields. I maintain a Python library on bitbucket called...
Went 280km/h (174mph) in a Porsche Panamera in Germany!
Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos. It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.
Linear Feedback Shift Registers for the Uninitiated, Part I: Ex-Pralite Monks and Finite Fields
Later there will be, I hope, some people who will find it to their advantage to decipher all this mess.
— Évariste Galois, May 29, 1832
I was going to call this short series of articles “LFSRs for Dummies”, but thought better of it. What is a linear feedback shift register? If you want the short answer, the Wikipedia article is a decent introduction. But these articles are aimed at those of you who want a little bit deeper mathematical understanding,...
Going back to Germany!
A couple of blog posts ago, I wrote that the decision to go to ESC Boston ended up being a great one for many different reasons. I came back from the conference energized and really happy that I went.
These feelings were amplified a few days after my return when I received an email from Rolf Segger, the founder of SEGGER Microcontroller (check out their very new website), asking if I would be interested in visiting their headquarters...
ESC Boston's Videos are Now Up
In my last blog, I told you about my experience at ESC Boston and the few videos that I was planning to produce and publish. Here they are, please have a look and any feedback (positive or negative) is appreciated.
Short HighlightThis is a very short (one minute) montage of some of the footage that I shot at the show & conference. In future shows, I absolutely need to insert clips here and there of engineers saying a few words about the conference (why they...
Back from ESC Boston
NOT going to ESC Boston would have allowed me to stay home, in my comfort zone.
NOT going to ESC Boston would have saved me from driving in the absolutely horrible & stressful Boston traffic1.
NOT going to ESC Boston would have saved me from having to go through a full search & questioning session at the Canada Customs on my return2.
2017/06/06 update: Videos are now up!So two days...
Launch of Youtube Channel: My First Videos - Embedded World 2017
I went to Embedded World 2017 in Nuremberg with an ambitious plan; I would make video highlights of several exhibits (booths) to be presented to the *Related sites audience. I would try to make the vendors focus their pitch on the essential in order to produce a one to three minutes video per booth.
So far my experience with making videos was limited to family videos, so I knew I had lots of reading to do and lots of Youtube videos and tutorials to watch. Trade shows are...
New Comments System (please help me test it)
I thought it would take me a day or two to implement, it took almost two weeks...
But here it is, the new comments systems for blogs, heavily inspired by the forum system I developed earlier this year.
Which means that:
- You can easily add images, either by drag and drop or through the 'Insert Image' button
- You can add MathML, TeX and ASCIImath equations and they will be rendered with Mathjax
- You can add code snippets and they will be highlighted with highlights.js
- You can edit...
Inside the Spartan-6: Using LUTs to optimize circuits
While building a small CPU on a Spartan-6 chip I came across the same old problem: my Verilog was mapping to a lot of slices . Way more then seems reasonable. So let's dig in and see what's really going on.
The J1 CPU (see Messing Around with a J1) is an amazingly streamlined design expressed in just over 100 lines of Verilog, and is reasonably compact at 150 Spartan-6 slices (half of that with the modifications described in the article). But the Picoblaze is...
VHDL tutorial - combining clocked and sequential logic
In an earlier article on VHDL programming ("VHDL tutorial" and "VHDL tutorial - part 2 - Testbench", I described a design for providing a programmable clock divider for a ADC sequencer. In this example, I showed how to generate a clock signal (ADCClk), that was to be programmable over a series of fixed rates (20MHz, 10MHz, 4MHz, 2MHz, 1MHz and 400KHz), given a master clock rate of 40MHz. A reader of that article had written to ask if it was possible to extend the design to...
Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA
Hi everyone! After a lot of hesitation and several failed attempts, I have finally entered the world of blogging. A little about myself : My name is Sriyash Caculo and I’m a third year undergrad student at BITS Pilani K.K. Birla Goa Campus pursuing a major in Electronics and Instrumentation engineering. Being an electronics engineer, I developed an interest in Digital Signal Processing and its implementation on hardware.
This blog-post is the first of many to come for the...
Running Average
The running average filter is a useful way to reduce noise in a system. One project I recently worked on required a 4 times frequency output from an encoder input. The problem was the encoder is mounted to the wheel of an old truck and bearing noise was making the original algorithm generate way too many pulses. The original algorithm worked, but the noise on the input made it useless.
I first implemented the moving average based on
Tools of the Trade: reading PDFs (and keeping bookmarks)
In this article I will take a look at the wonderful MuPDF viewer and present a small modification that saves bookmarks alongside the pdf files, making it infinitely more useful.
Some days I sit down to work and wonder how anything ever gets done. A simple example. When I work on an FPGA design, I wind up with 3 or 4 screens full of documentation, generally in PDF format. There are the Xilinx manuals, the various tool manuals, language reference manuals, you name it. While...
Dealing With Fixed Point Fractions
Fixed point fractional representation always gives me a headache because I screw it up the first time I try to implement an algorithm. The difference between integer operations and fractional operations is in the overflow. If the representation fits in the fixed point result, you can not tell the difference between fixed point integer and fixed point fractions. When integers overflow, they lose data off the most significant bits. When fractions overflow, they lose data off...
Shared-multiplier polyphase FIR filter
Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier
Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.
IntroductionA polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...
Learning VHDL - Basics
Since FPGA are becoming more accessible to the hobbyist, learning how to use them can be really useful for certain applications, like DSP and video generation; moreover, engineers that are able to code in VHDL/Verilog are always requested on the job market.
In this tutorial I will cover the basics of Xilinx ISE and VHDL. I willl base my code on the Basys2 board from Digilent: it is really cheap (especially for students) and has a lot of features on board, as you can see from the picture...
MyHDL FPGA Tutorial II (Audio Echo)
Introduction
This tutorial will walk through an audio echo that can be implemented on an FPGA development board. This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial. This project will require an FPGA board with an audio codec and the interface logic to the audio codec.
Review the Previous TutorialThe previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board. In that tutorial we introduced the basics of a MyHDL module....
An absolute position encoder VHDL core
Introduction
Let's consider motorized systems controlled by electronics. A closed loop architecture looks like this:
The following components are involved:
- the motor itself (DC, stepper ...),
- the controller, in charge of computing position according to the whole system state,
- the driver board in charge of generating signals and power for the motor,
- the position encoder, the subject of this post.
Most of the time, there is a difference between the position the system...
Discrete-Time PLLs, Part 1: Basics
Design Files: Part1.slx
Hi everyone,
In this series of tutorials on discrete-time PLLs we will be focusing on Phase-Locked Loops that can be implemented in discrete-time signal proessors such as FPGAs, DSPs and of course, MATLAB.
In the first part of the series, we will be reviewing the basics of continuous-time baseband PLLs and we will see some useful mathematics that will give us insight into the inners working of PLLs. In the second part, we will focus on...
How to start in FPGA development? - Simulation software tools
Introduction
This post is related to the first post How to start in FPGA development? - Some tips which aimed to show other options to work on the simulation of your project. In this first approach will be explained some advantages and disadvantages of using Xilinx ISE (+ModelSim) or using ModelSim, Precision and Xilinx ISE. And finally my opinion of which are the ones I...
Shared-multiplier polyphase FIR filter
Keywords: FPGA, interpolating decimating FIR filter, sample rate conversion, shared multiplexed pipelined multiplier
Discussion, working code (parametrized Verilog) and Matlab reference design for a FIR polyphase resampler with arbitrary interpolation and decimation ratio, mapped to one multiplier and RAM.
IntroductionA polyphase filter can be as straightforward as multirate DSP ever gets, if it doesn't turn into a semi-deterministic, three-legged little dance between input, output and...
How to start in FPGA development? - Some tips
IntroductionThe aim of this tutorial is to show some useful tips for people like me that one day started from zero to work with FPGA's. Why FPGA's? Because they are easy to use and they are not too expensive, and they are usually used in lab courses to let students "play" with them.
1: How to choose the right FPGA?As you may know there are a lot of different FPGA's, brands and models. How to choose the right one? It's very difficult to say that before knowing which will be the...
The Spartans
The latest release of the Xilinx Spartan family is the Spartan6 line of FPGAs. It has been awhile since the last major Spartan released, the Spartan3, but this last year Xilinx released the Spartan6. The Xilinx Spartan family is the low cost FPGAs compared to the higher cost and high performance Virtex family. The Spartan family is derived from the Virtex architecture with some changes to reduce the cost. The Spartan3 FPGAs were derived from the Virtex-II architecture. Since the Spartan3...
Linear Feedback Shift Registers for the Uninitiated, Part I: Ex-Pralite Monks and Finite Fields
Later there will be, I hope, some people who will find it to their advantage to decipher all this mess.
— Évariste Galois, May 29, 1832
I was going to call this short series of articles “LFSRs for Dummies”, but thought better of it. What is a linear feedback shift register? If you want the short answer, the Wikipedia article is a decent introduction. But these articles are aimed at those of you who want a little bit deeper mathematical understanding,...
StrangeCPU #4. Microcode
Summary:Sliding windows containing runs of microcode.
Table of Contents:-
Part 1: A new CPU - technology review, re-examination of the premises; StrangeCPU concepts; x86 notes.
-
Part 2: Sliding-Window Token Machines, an in-depth exploration of this curious technology; ARM notes.
Half-band filter on Xilinx FPGA
1. DSP48 Slice in Xilinx FPGA
There are many DSP48 Slices in most Xilinx® FPGAs, one DSP48 slice in Spartan6® FPGA is shown in Figure 1, the structure may different depending on the device, but broadly similar.
Figure 1: A whole DSP48A1 Slice in Spartan6 (www.xilinx.com)
2. Symmetric Systolic Half-band FIRFigure 2: Symmetric Systolic Half-band FIR Filter
3. Two-channel Symmetric Systolic Half-band FIRFigure 3: 2-Channel...
Two jobs
For those of you following closely embeddedrelated and the other related sites, you might have noticed that I have been less active for the last couple of months, and I will use this blog post to explain why. The main reason is that I got myself involved into a project that ended up using a better part of my cpu than I originally thought it would.
edit - video of the event:
I currently have two jobs: one as an electrical/dsp engineer recycled as a web publisher and the other...
Went 280km/h (174mph) in a Porsche Panamera in Germany!
Those of you who've been following my blog lately already know that I am going through some sort of mid-life crisis that involves going out there to meet people and make videos. It all started with Embedded World early this year, then continued at ESC Boston a couple of months ago and the latest chapter just concluded as I returned from Germany after spending a week at SEGGER's headquarters to produce a video to highlight their 25th anniversary.
New Design - Finally!
For those of you who are familiar with my work, you already know that FPGARelated.com is not the only engineering web site that I publish. I also publish DSPRelated.com and EmbeddedRelated.com. Those two web sites have been on a new design for quite some time now and porting the new design to FPGARelated.com has been on my todo list for too long! I am glad today to announce that I have finally found the time to apply the more modern design to FPGARelated.com.
Thank you...
New Discussion Group: DSP & FPGA
I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to: fpgadsp-subscribe@yahoogroups.com
As usual, it should take a few weeks before there are enough members for interesting discussions to get started.
