Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
Mathematics and Cryptography
Cryptographic math can look intimidating, but this roundup trims it to what FPGA engineers actually need. It groups concise articles on number theory and elliptic curves, focusing on polynomial math over Galois fields, FPGA-friendly inversion and one-clock-cycle techniques, and elliptic-curve key exchange and digital signatures. Read this to learn which subroutines to implement first and how to turn math into Verilog or VHDL.
Elliptic Curve Digital Signatures
Elliptic curve digital signatures deliver compact, strong message authentication by combining a hash of the message with elliptic curve point math. This post walks through the standard sign and verify equations, showing why recomputing a point R' yields the same x coordinate only when the hash matches. It also explains the Nyberg-Rueppel alternative that removes modular inversion and an FPGA-friendly trick of transmitting point D to avoid integer modular arithmetic.
Elliptic Curve Key Exchange
Elliptic Curve key exchange gives a fresh secret for every session so past messages stay safe even if one key is discovered. This post walks through an ElGamal-style ephemeral exchange and the MQV protocol, showing how MQV mixes static and random keys to provide mutual authentication and forward secrecy. It also explains how MQV can be implemented using only curve operations to save FPGA area and why erasing ephemeral values matters.
Discrete-Time PLLs, Part 1: Basics
In this series of tutorials on discrete-time PLLs we will be focusing on Phase-Locked Loops that can be implemented in discrete-time signal proessors such as FPGAs, DSPs and of course, MATLAB.
Polynomial Inverse
One of the important steps of computing point addition over elliptic curves is a division of two polynomials.
One Clock Cycle Polynomial Math
Error correction codes and cryptographic computations are most easily performed working with GF(2^n)
Elliptic Curve Cryptography
Secure online communications require encryption. One standard is AES (Advanced Encryption Standard) from NIST. But for this to work, both sides need the same key for encryption and decryption. This is called Private Key encryption.
An absolute position encoder VHDL core
In this article, Fabien Le Mentec explains how to implement a unique VHDL core addressing absolute position encoder interfaces. He reviews existing instruments in use or being developed and considers their specific requirements. He also looks for details in current implementations and considers the projects to come so that the implementation can be designed to be extensible. The VHDL core dubbed absenc features both ENDAT, BISS and SSI interface. Due to its architecture, new interfaces are easily added. Also, the 3 interfaces can be enabled at synthesis while 1 is selected at runtime. As much as possible, resources common to the different interfaces are shared (counters, comparators…).
Helping New Bloggers to Break the Ice: A New Ipad Pro for the Author with the Best Article!
Breaking the ice can be tough. Over the years, many individuals have asked to be given access to the blogging interface only to never post an article.
StrangeCPU #1. A new CPU
This post rethinks call instructions by factoring call targets out of every callsite and replacing them with tiny tokens. Victor Yurkovsky introduces StrangeCPU, a bytecode CPU that uses 8-bit tokens plus a static sliding-window token table to give byte-long calls full 32-bit reach while dramatically reducing code size. The article includes rationale, tradeoffs, a simple proof-of-concept x86 interpreter, and the basic lookup equation for hardware implementation.
Crowdfunding Articles?
Many of you have the knowledge and talent to write technical articles that would benefit the EE community. What is missing for most of you though, and very understandably so, is the time and motivation to do it.
But what if you could make some money to compensate for your time spent on writing the article(s)? Would some of you find the motivation and make the time?
I am thinking of implementing a system/mechanism that would allow the EE community to...
SEGGER's 25th Anniversary Video
Stephane Boucher spent a week at SEGGER's headquarters and distilled that visit into a tight, two-minute 25th anniversary video. The post highlights rising production value, thanks to softbox lighting and a two-camera setup that allows seamless wide-to-tight cuts and emotional close-ups. Stephane invites readers to watch full screen, leave feedback and thumbs-up on YouTube, and suggests future coverage like product launches or companies with happy engineers.
Ancient History
The other day I was downloading an IDE for a new (to me) OS. When I went to compile some sample code, it failed. I went onto a forum, where I was told "if you read the release notes you'd know that the peripheral libraries are in a legacy download". Well damn! Looking back at my previous versions I realized I must have done that and forgotten about it. Everything changes, and keeping up with it takes time and effort.
When I first started with microprocessors we...
FPGA skills for the modern world
FPGA demand is booming across industries from automotive to edge AI, and employers want engineers who can think in hardware. This post explains the mindset shift to RTL-level, concurrent design, waveform-based debugging with ILAs, and modern verification flows. It also highlights the practical skills that make you marketable, including HDLs, SoC/Linux integration, RISC-V know-how, and high-speed design techniques.
What to See at Embedded World 2019
Skip the overwhelm at Embedded World 2019, Stephane Boucher lays out a practical preview of what to see and how to prioritize your time. The post helps embedded engineers focus on demos, vendor booths, and sessions that matter without getting lost on the show floor. Read it to plan a short, efficient visit that maximizes technical takeaways and networking opportunities.
Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!
This will be my first time attending this show and I must say that I am excited. I am bringing with me my cameras and other video equipment with the intention to capture as much footage as possible and produce a (hopefully) fun to watch 'highlights' video. I will also try to film as many demos as possible and share them with you.
I enjoy going to shows like this one as it gives me the opportunity to get out of my home-office (from where I manage and run the *Related sites) and actually...
Feedback Controllers - Making Hardware with Firmware. Part 2. Ideal Model Examples
An engineer's guide to building ideal continuous-time models for hardware emulation, using TINA Spice, MATLAB and Simulink to validate controller and circuit behavior. The article shows how a passive R-C network can be emulated by an amplifier, a current measurement and a summer, with Spice, MATLAB and Simulink producing coincident Bode responses. Small phase differences between MATLAB and Simulink are noted, and sampled-data issues are slated for the next installment.
3 Good News
Stephane Boucher reports three quick wins for the EmbeddedRelated community: two sponsors have seeded a $1,000 rewards pool, the site now serves all pages over HTTPS, and the new forums have their first active discussions. If you want a share of the sponsor-funded rewards, jump into the forums and check the Vendors Directory for opportunities. Stay tuned for more updates.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
Michael Morris shows how to pack many asynchronous serial receivers into the area of a single UART by treating FPGA LUTs as writable storage and sharing logic. Using a 4-bit channel counter, microprogrammed state machine, and time-multiplexed baud/sample resources, he fits 16 receive channels (12 used for Caller ID) into a Spartan II XC2S30 and explains input synchronization, filtering, and the multi-channel FIFO approach.
Makefiles for Xilinx Tools
Building a bitstream from HDL is messy, and Victor Yurkovsky lays out a minimal, practical makefile workflow for Xilinx ISE and XST. He shows a simple project layout, techniques to tame ISE's generated logs and temps, and a ready-to-clone repo; an LED blinker example builds to bitstream in under 20 seconds on his machine. Use it as a pragmatic starting point for command-line FPGA builds.
Embedded World 2018 - The Interviews
Stephane Boucher brought video gear to Embedded World 2018 and teamed up with Jacob Beningo to capture concise vendor interviews that focus on real product news. The videos showcase Percepio's new Tracealyzer with a drone demo, Intrinsic ID's method for creating device-unique IDs from manufacturing variations, and SEGGER's broader toolset including embOS now certified by TÜV SÜD. Watch for short demos and expert explanations.
Embedded World 2018 - More Videos!
Two cinematic videos from Embedded World 2018 turn the show floor into slow-motion, stabilized footage using a Zhiyun Crane gimbal and a Sony a6300. One is a SEGGER booth highlights piece featuring Rolf Segger and Axel Wolf, the other is a roaming montage with appearances from Jacob Beningo, Micheal Barr, and Alan Hawse. Stephane asks viewers to enable audio and share feedback.
Use Microprogramming to Save Resources and Increase Functionality
Microprogramming can rescue an overfull FPGA, Michael Morris shows, by compressing control logic and time-multiplexing FIFO storage. He replaces an ABEL state machine with a small microprogram ROM that uses block RAM for deep Rx/Tx FIFOs and LUT RAM for pointers and counters, freeing about 25 percent of the device. The article includes Verilog comparisons, resource tables, and a microassembler link to reproduce the approach.
Back from ESC Boston
Stephane nearly skipped ESC Boston, but going turned into a productive mix of networking, informal meetups, and on-the-floor filming. He captures candid encounters with speakers and vendors, learns how small shows differ from larger expos, and outlines practical follow-ups like booth highlight videos and speaker hospitality suggestions. The post is an encouraging read for engineers weighing the value of regional conferences and DIY event coverage.
SEGGER's 25th Anniversary Video
Stephane Boucher spent a week at SEGGER's headquarters and distilled that visit into a tight, two-minute 25th anniversary video. The post highlights rising production value, thanks to softbox lighting and a two-camera setup that allows seamless wide-to-tight cuts and emotional close-ups. Stephane invites readers to watch full screen, leave feedback and thumbs-up on YouTube, and suggests future coverage like product launches or companies with happy engineers.
How to start in FPGA development? - Some tips
Starting from zero, this practical primer walks new FPGA users through the early decisions and habits that make projects work. Nuria Orduna covers how to pick a device, sketch a clear dataflow, prototype in MATLAB or C, organize VHDL entities versus functions, and use ModelSim .do files and testbenches to debug before programming the board. Read it for concise, hands-on starting points.
In TCL FPGA Wizards Trust
In TCL FPGA wizards trust. The best way to learn TCL is exposure therapy which we will be doing here using two examples: One for creation of a project with synthesis and implementation steps and another for simulation.
Crowdfunding Articles?
Many of you have the knowledge and talent to write technical articles that would benefit the EE community. What is missing for most of you though, and very understandably so, is the time and motivation to do it.
But what if you could make some money to compensate for your time spent on writing the article(s)? Would some of you find the motivation and make the time?
I am thinking of implementing a system/mechanism that would allow the EE community to...
