Homebrew CPUs: Color Languages

Victor Yurkovsky June 17, 2015
Color Languages

Here on bizarro we program using -- get this – text!  Our other senses - hearing, touch, smell, are not used at all. Even our visual perception is greatly underutilized - we just use two-dimensional text on a flat display a foot in front of our eyes.

Color is just beginning to be used, although in a lame syntax coloring way only. Granted, it makes it easier to detect stupid syntax errors such as misspelled keywords. Sadly, color carries zero semantic or...


Homebrew CPUs: Messing around with a J1

Victor Yurkovsky May 29, 2015

In this article I will examine James Bowman's excellent J1 CPU; I will then proceed to mess around with various parts of it, making it smaller, more appropriate to my particular application, and possibly faster.  I hope this will show you how easy it is to fiddle around with homemade CPUs and encourage you to make something weird and wonderful.

J1 CPU

My hat is off to James Bowman.  J1 is pretty cool.  It is a stack machine; it executes instructions in one cycle, it is...


Makefiles for Xilinx Tools

Victor Yurkovsky May 12, 20155 comments

Building a bitstream from an HDL is a complicated process that requires the cooperation of a lot of tools.  You can hide behind an IDE or grow a pair and use command line tools and a makefile to tie your build process together.  I am not a huge fan of makefiles either (I believe a language should be expressive enough to automate the build process), but the alternatives are dismal. 

Command-line driven workflow is easier on the hands and faster.  The example...


Use a Simple Microprogram Controller (MPC) to Speed Development of Complex Microprogrammed State Machines

Michael Morris April 18, 20152 comments
Introduction

This article will describe a synthesizable HDL-based microprogram controller (MPC), or microprogram sequencer (MPS), that can be used to provide the control of a microprogrammed state machine. Unlike the microprogrammed state machines that I described in my previous two articles, "Use Microprogramming to Save Resources and Add Functionality" and "Fit Sixteen (or more) Asynchronous Serial Receivers in the Area of a Standard UART", many microprogrammed state machines will...


Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver

Michael Morris March 29, 20155 comments
Introduction

This article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.

To stay true to the original design, I...


Use Microprogramming to Save Resources and Increase Functionality

Michael Morris March 21, 2015
Introduction

Microprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...


I don’t often convert VHDL to Verilog but when I do ...

Christopher Felton December 24, 20142 comments
VHDL to Verilog

I don’t often convert VHDL to Verilog but when I do it is not the most exciting task in the world (that is an understatement).  For the most part I am HDL agnostic.  Well that is not true, I have a strong preference for MyHDL, and an insubstantial preference for VHDL over Verilog.  The choice of HDL for a project is often complicated, irrational, sometimes rational, but most often random.  It is often not a choice of the developer - for...


Point of View

Christopher Felton August 28, 20146 comments

I was caught of guard when someone commented:

"when a FIR filter is full of multiple loops and complex code, something is wrong"

The comment was made during an informal discussion on alternative hardware description languages (HDL) and was targeted to the straightforward FIR filter implemented in MyHDL

(different FIR description simulation results) 

Personally, (and...


MyHDL Presentation Examples

Christopher Felton August 26, 2014

The last two years I presented at EELive.  The first year as an overview of MyHDL and a strong case why you should be using MyHDL as your hardware description language (HDL) [paper].  The second year was an introduction to three alternative HDLs (alt.hdl), including MyHDL.  I also presented at a regional Python conferene: pyohio.  At the Python conference I presented...


Spline interpolation

Markus Nentwig May 11, 20146 comments

A cookbook recipe for segmented y=f(x) 3rd-order polynomial interpolation based on arbitrary input data. Includes Octave/Matlab design script and Verilog implementation example. Keywords: Spline, interpolation, function modeling, fixed point approximation, data fitting, Matlab, RTL, Verilog

Introduction

Splines describe a smooth function with a small number of parameters. They are well-known for example from vector drawing programs, or to define a "natural" movement path through given...


Running Average

Mike February 15, 20166 comments

The running average filter is a useful way to reduce noise in a system.  One project I recently worked on required a 4 times frequency output from an encoder input.  The problem was the encoder is mounted to the wheel of an old truck and bearing noise was making the original algorithm generate way too many pulses.  The original algorithm worked, but the noise on the input made it useless.

I first implemented the moving average based on


Sensors Expo - Trip Report & My Best Video Yet!

Stephane Boucher August 3, 20183 comments

This was my first time at Sensors Expo and my second time in Silicon Valley and I must say I had a great time.  

Before I share with you what I find to be, by far, my best 'highlights' video yet for a conference/trade show, let me try to entertain you with a few anecdotes from this trip.  If you are not interested by my stories or maybe don't have the extra minutes needed to read them, please feel free to skip to the end of this blog post to watch the...


Use Microprogramming to Save Resources and Increase Functionality

Michael Morris March 21, 2015
Introduction

Microprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...


Going back to Germany!

Stephane Boucher June 13, 20176 comments

A couple of blog posts ago, I wrote that the decision to go to ESC Boston ended up being a great one for many different reasons.  I came back from the conference energized and really happy that I went.  

These feelings were amplified a few days after my return when I received an email from Rolf Segger, the founder of SEGGER Microcontroller (check out their very new website), asking if I would be interested in visiting their headquarters...


Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver

Michael Morris March 29, 20155 comments
Introduction

This article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.

To stay true to the original design, I...


How precise is my measurement?

Sam Shearman March 28, 20183 comments

Some might argue that measurement is a blend of skepticism and faith. While time constraints might make you lean toward faith, some healthy engineering skepticism should bring you back to statistics. This article reviews some practical statistics that can help you satisfy one common question posed by skeptical engineers: “How precise is my measurement?” As we’ll see, by understanding how to answer it, you gain a degree of control over your measurement time.

An accurate, precise...

3 Good News

Stephane Boucher March 9, 20161 comment
Good News #1

Last week, I announced a new and ambitious reward program that will be funded by the new Vendors Directory.

This week, I am happy to announce that we have our firsts two sponsors!  Quantum Leaps & Abelon Systems have agreed to pay the sponsorship fee to be listed in the new Vendors Directory.  Because of their support, there is now some money in the reward pool ($1,000) and enough to pay for the firsts 500 'beers' awarded.  Please...


Windows XP and Win32 - the Platform of the Future!

Victor Yurkovsky October 6, 20132 comments

Over the past decade I often wondered why anyone uses Windows.  It's just so... proprietary.  And pedestrian.  As I grew up my OS of choice went nothing to CPM to DOS (on Apple ][), GEM on Atari ST,  MS-DOS, DOS extenders, Mac OS, Windows NT, Windows XP, Linux...  Now, I again find myself a fan of Windows XP, the platform of the future.  (I am still a fan of bare metal, of course).Maybe I am not totally serious, but I, a self-proclaimed freedom lover and...


Linear Feedback Shift Registers for the Uninitiated, Part II: libgf2 and Primitive Polynomials

Jason Sachs July 17, 2017

Last time, we looked at the basics of LFSRs and finite fields formed by the quotient ring \( GF(2)[x]/p(x) \).

LFSRs can be described by a list of binary coefficients, sometimes referred as the polynomial, since they correspond directly to the characteristic polynomial of the quotient ring.

Today we’re going to look at how to perform certain practical calculations in these finite fields. I maintain a Python library on bitbucket called...


Feedback Controllers - Making Hardware with Firmware. Part I. Introduction

Steve Maslen August 22, 2017
Introduction to the topic 

This is the 1st in a series of articles looking at how we can use DSP and Feedback Control Sciences along with some mixed-signal electronics and number-crunching capability (e.g. FPGA), to create arbitrary (within reason) Electrical/Electronic Circuits with real-world connectivity. Of equal importance will be the evaluation of the functionality and performance of a practical design made from modestly-priced state of the art devices.

  • Part 1: